x95840 Intersil Corporation, x95840 Datasheet

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x95840

Manufacturer Part Number
x95840
Description
Quad Digital Controlled Potentionmeters Xdcp? ; Low Noise/low Power/i2c? Bus/256 Taps
Manufacturer
Intersil Corporation
Datasheet

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Low Noise/Low Power/I
The X95840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the four
DCP’s IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Ordering Information
X95840WV20I-2.7*
X95840WV20IZ-2.7*
(Note)
X95840UV20I-2.7*
X95840UV20IZ-2.7*
(Note)
*Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2
C bus interface. Each potentiometer has an associated
PART NUMBER
X95840WV G
X95840WV Z G
X95840UV G
X95840UV Z G
MARKING
PART
®
1
2
C
RESISTANCE
Data Sheet
®
OPTION
10kΩ
10kΩ
50kΩ
50kΩ
Bus/256 Taps
20 Ld TSSOP
20 Ld TSSOP
(Pb-free)
20 Ld TSSOP
20 Ld TSSOP
(Pb-free)
PACKAGE
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
1-888-INTERSIL or 1-888-468-3774
Quad Digital Controlled Potentiometers (XDCP™)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Four Potentiometers in One Package
• 256 Resistor Taps-0.4% Resolution
• I
• Wiper Resistance: 70Ω Typical @ 3.3V
• Non-Volatile Storage of Wiper Position
• Standby Current < 5µA Max
• Power Supply: 2.7V to 5.5V
• 50kΩ, 10kΩ Total Resistance
• High Reliability
• 20 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinouts
- Three address pins, up to eight devices/bus
- Endurance: 150,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ 75°C
2
C Serial Interface
All other trademarks mentioned are the property of their respective owners.
|
July 5, 2006
Intersil (and design) is a registered trademark of Intersil Americas Inc.
RW3
GND
RW2
SDA
RH3
SCL
RH2
RL3
RL2
A2
(20 LD TSSOP)
1
2
3
4
5
6
7
8
9
10
TOP VIEW
X95840
20
19
18
17
16
15
14
13
12
11
RW0
RL0
RH0
WP
V
A1
A0
RH1
RL1
RW1
CC
X95840
FN8213.2

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x95840 Summary of contents

Page 1

... Data Sheet 2 ® Low Noise/Low Power/I C The X95840 integrates four digitally controlled potentiometers (XDCP monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the ...

Page 2

... RW1 12 RL1 13 RH1 RH0 19 RL0 20 RW0 2 X95840 POWER-UP, INTERFACE, CONTROL AND StAtus LOGIC NON-VOLATILE REGISTERS WP GND “High” terminal of DCP3 “Low” terminal of DCP3 “Wiper” terminal of DCP3 Device address for the interface interface clock ...

Page 3

... Roffset Offset (Note 10) R DCP to DCP Matching MATCH (Note 13) TC Resistance Temperature Coefficient R (Note 14) 3 X95840 Recommended Operating Conditions Temperature Range (Industrial -40°C to 85° 2.7V to 5.5V CC +0.3 Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CC Wiper Current of Each DCP ±3.0mA CC TEST CONDITIONS W, U versions respectively V = 3.3V @ 25° ...

Page 4

... Clock LOW Time LOW t Clock HIGH Time HIGH t START Condition Setup SU:STA Time t START Condition Hold Time From SDA falling edge crossing 30 HD:STA 4 X95840 TEST CONDITIONS 400kHz; SDA = Open; (for , SCL Active, Read and Volatile Write States only 400kHz ...

Page 5

... SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) 5 X95840 TEST CONDITIONS From SDA exiting the 30 SCL rising edge crossing 30 From SCL rising edge crossing 70 entering the 30 window. CC rising edge crossing 30 ...

Page 6

... Write by the user, unless Acknowledge Polling is used the time from a WC valid STOP condition at the end of a Write sequence write cycle. 6 X95840 Clk 1 t SU:WPA and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the ...

Page 7

... T = 25° 2. 85°C CC -0.15 -0 100 150 TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 0.4 0.35 0.3 2.7V 0.25 0.2 5.5V 0.15 -40 - TEMPERATURE (°C) FIGURE 5. ZSerror vs TEMPERATURE 7 X95840 1 25°C CC 1.4 1.2 1.0 0.8 0 85°C 0.2 CC 0.0 200 250 0 2. -40°C CC 0.2 0.1 0 -0 85° ...

Page 8

... TEMPERATURE (°C) FIGURE 9. END TO END R % CHANGE vs TOTAL TEMPERATURE -15 - 107 132 157 TAP POSITION (DECIMAL) FIGURE 11. TC FOR Rheostat MODE IN ppm 8 X95840 (Continued 25°C 0.4 CC 0.3 0.2 0.1 0 -0.1 -0 85° -40°C CC -0.5 32 182 232 FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR ...

Page 9

... RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the X95840 is being powered up, all four WRs are reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. Soon after the power supply voltage becomes large enough for reliable non-volatile ...

Page 10

... Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 15). On power up of the X95840 the SDA pin is in the input mode. 2 All I ...

Page 11

... Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the X95840 responds with an ACK. At this time, if the Data Byte written only to volatile registers, then the device enters its standby state. If the Data Byte written also to non-volatile memory, the X95840 begins its internal write cycle to non-volatile memory ...

Page 12

... Signals from the Slave 12 X95840 pointer “rolls over” to 00h, and the device continues to output data for each ACK received. The byte at address 00001000 bin (8 decimal) determines if the Data Bytes being read are from volatile or non-volatile memory. See “Memory Description” on page 9. ...

Page 13

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 X95840 MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A ...

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