ZL9101EVAL1Z Intersil, ZL9101EVAL1Z Datasheet

ZL9101EVAL1Z

Manufacturer Part Number

ZL9101EVAL1Z

Description

EVALUATION BOARD 1 ZL9101

Manufacturer

Intersil

Datasheets

1.ZL9101EVAL1Z.pdf (17 pages)

2.ZL9101EVAL1Z.pdf (11 pages)

Specifications of ZL9101EVAL1Z

Main Purpose

DC/DC, Step Down

Outputs And Type

1, Non-Isolated

Voltage - Output

0.6 ~ 4 V

Current - Output

12A

Voltage - Input

12V

Regulator Topology

Buck

Frequency - Switching

615kHz

Board Type

Fully Populated

Utilized Ic / Part

ZL9101

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Power - Output

Current page: 1 of 17
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Digital DC/DC PMBus 12A Module

ZL9101M

The ZL9101M is a 12A variable output step-down

PMBus-compliant digital power supply. Included in the module

is a high performance digital PWM controller, power MOSFETs,

an inductor, and all the passive components required for a

complete DC/DC power solution. The ZL9101M operates over

a wide input voltage range and supports an output voltage

range of 0.6V to 4V, which can be set by external resistors or

via PMBus. This high efficiency power module is capable of

delivering 12A. Only bulk input and output capacitors are

needed to finish the design. The output voltage can be

precisely regulated to as low as 0.6V with ±1% output voltage

regulation over line, load, and temperature variations.

The ZL9101M features internal compensation, internal

soft-start, auto-recovery overcurrent protection, an enable

option, and pre-biased output start-up capabilities.

The ZL9101M is packaged in a thermally enhanced, compact

(15mmx15mm) and low profile (3.5mm) over-molded QFN

package module suitable for automated assembly by standard

surface mount equipment. The ZL9101M is Pb-free and RoHS

compliant.

NOTE: Figure 1 represents a typical implementation of the ZL9101M. For PMBus operation, it is recommended to tie the enable pin (EN) to SGND.

April 8, 2011

FN7669.2

POWER GOOD OUTPUT

Notes:

1. The I

2. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of

devices connected). The 10k

Please refer to the Digital-DC Bus section for more details.

3. Additional capacitance may be required to meet specific transient response targets

4. The VR, V25, VDRV, and VDD capacitors should be placed no further than 0.5 cm from the pin.

ENABLE

C/SMBus requires pull-up resistors. Please refer to the I

Ext Sync

4.5V TO 6.5V

DDC Bus

C/SMBus

default value, assuming a maximum of 100pF per device, provides the necessary 1µs pull-up rise time.

DRV

SYNC

SCL

SDA

DDC

FIGURE 1. 12A APPLICATION CIRCUIT

1-888-INTERSIL or 1-888-468-3774

10µF

16V

ZL9101M

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

4.7µF

16V

C/SMBus specifications for more details.

4.7µF

16V

(EPAD)

PGND

(EPAD)

VOUT

VIN

Features

• Complete Digital Switch Mode Power Supply

• Fast Transient Response

• External Synchronization

• Output Voltage Tracking

• Current Sharing

• Programmable Soft-start Delay and Ramp

• Overcurrent/Undercurrent Protection

• PMBus Compliant

Applications

• Server, Telecom, and Datacom

• Industrial and Medical Equipment

• General Purpose Point of Load

Related Literature

• See AN2033, “Zilker Labs PMBus Command Set - DDC

• See AN2034, “Configuring Current Sharing on the ZL2004

10µF

16V

Products”

and ZL2006”

All other trademarks mentioned are the property of their respective owners.

Intersil (and design) is a registered trademark of Intersil Americas Inc.

3 x 47µF

16V

4.5V TO 13.2V

2 x 22µF

16V

RTN

OUT

Related parts for ZL9101EVAL1Z

ZL9101EVAL1Z Summary of contents

Page 1

... FIGURE 1. 12A APPLICATION CIRCUIT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved All other trademarks mentioned are the property of their respective owners ...

Page 2

Pin Configuration PGND V25 VDD VDRV PIN LABEL TYPE 1 SDA I/O Serial data. 2 SCL I/O Serial clock Serial address select pin. Used to assign unique SMBus address to each module. 4 SYNC I/O Clock synchronization. ...

Page 3

... Add “-T*” suffix for tape and reel. Please refer to 2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by EU exemption 5 (Pb in glass of cathode ray tubes, electronic components and fluorescent tubes) ...

Page 4

Table of Contents Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

... Thermal Resistance (Typical) QFN Package (Notes Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Input Supply Voltage Range, V Input Supply For Controller, V Driver Supply Voltage, V Output Voltage Range, V ...

Page 6

Electrical Specifications V over the operating temperature range, -40°C to +85°C. PARAMETER Soft-start Ramp Duration Accuracy (Note 11) DYNAMIC CHARACTERISTICS Voltage Change for Positive Load Step Voltage Change for Negative Load Step OSCILLATOR AND SWITCHING CHARACTERISTICS Switching Frequency Range Maximum ...

Page 7

Electrical Specifications V over the operating temperature range, -40°C to +85°C. PARAMETER Thermal Protection Threshold (Controller Junction Temperature) Thermal Protection Hysteresis NOTES: 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. ...

Page 8

Typical Performance Curves 0 0.1 0.2 0.3 0.4 0 -10 - 12V IN - 1.2V OUT I STEP = 6A to 12A OUT -25 SLEW 2.5A/µs -30 FIGURE 6. DYNAMIC RESPONSE, LOADING -0.2 ...

Page 9

Functional Description Output Voltage Selection The output voltage may be set to a voltage between 0.6V and 4.0V provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding ...

Page 10

Adaptive Diode Emulation Adaptive diode emulation mode turns off the low-side FET gate drive at low load currents to prevent the inductor current from going negative, reducing the energy losses and increasing overall efficiency. Diode emulation is available to single-phase ...

Page 11

If a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare ...

Page 12

TABLE 2. SMBus ADDRESS RESISTOR SELECTION R SA0 61.9 68.1 75 82.5 90.9 100 Digital-DC Bus The Digital-DC Communications (DDC) bus is used to communicate between Zilker Labs Digital-DC modules and devices. This dedicated bus provides the communication channel between ...

Page 13

PCB layout. Upon system start-up, the module with the lowest member position as selected in ISHARE_CONFIG is defined as the reference module. The remaining modules are members. The ...

Page 14

Undesirable results may be observed if the device’s V supply drops below 3.0V DD during this process. TABLE 3. SNAPSHOT_CONTROL ...

Page 15

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...

Page 16

Package Outline Drawing L21.15x15 21 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 0, 10/10 PIN 1 INDEX AREA 101112 15.0±0.2 15.8±0.2 TOP ...

Page 17

TYPICAL RECOMMENDED LAND PATTERN 0.0 1.2 1.8 3.8 4.4 5.8 STENCIL PATTERN WITH SQUARE PADS-2 ...

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