PIC24F04KA201-I/SS Microchip Technology, PIC24F04KA201-I/SS Datasheet - Page 57

• Manufacturer Part Number: PIC24F04KA201-I/SS
• Description: IC PIC MCU FLASH 512KX4 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA201-I/SS

• Core Size: 16-Bit
• Program Memory Size: 4KB (1.375K x 24)
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Number Of I /o: 18
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC24
• No. Of I/o's: 18
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.3
The PIC24F04KA201 family devices implement a BOR
circuit, which provides the user several configuration
and power-saving options. The BOR is controlled by
the <BORV1:BORV0> and (BOREN<1:0>) Configura-
tion bits (FPOR<6:5,1:0>). There are a total of four
BOR configurations, which are provided in Table 6.3.1.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of V
reset the device. The chip will remain in BOR until V
rises above threshold.
If the Power-up Timer is enabled, it will be invoked after
V
in Reset for an additional time delay, T
below the threshold while the power-up timer is running.
The chip goes back into a BOR and the Power-up Timer
will be initialized. Once V
the Power-up Timer will execute the additional time
delay.
BOR and the Power-up Timer are independently
configured. Enabling the BOR Reset does not
automatically enable the PWRT.
6.3.1
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<13>). Setting SBOREN
enables the BOR to function as previously described.
Clearing the SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise, it is
read as ‘0’.
Placing BOR under software control gives the user the
additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change the BOR configuration. It also allows the user
to tailor the incremental current that the BOR con-
sumes. While the BOR current is typically very small, it
may have some impact in low-power applications.
© 2009 Microchip Technology Inc.
DD
Note:
rises above the threshold; it, then, will keep the chip
Brown-out Reset (BOR)
SOFTWARE ENABLED BOR
Even when the BOR is under software
control, the BOR Reset voltage level is still
set by the BORV1:BORV0 Configuration
bits. It can not be changed in software.
DD
below the set threshold point will
DD
rises above the threshold,
PWRT
, if V
DD
drops
Preliminary
DD
PIC24F04KA201 FAMILY
6.3.2
When BOR is enabled, the BOR bit (RCON<1>) is
always reset to ‘1’ on any BOR or POR event. This
makes it difficult to determine if a BOR event has
occurred just by reading the state of BOR alone. A
more reliable method is to simultaneously check the
state of both POR and BOR. This assumes that the
POR and BOR bits are reset to ‘0’ in the software
immediately after any POR event. If the BOR bit is ‘1’
while POR is ‘0’, it can be reliably assumed that a BOR
event has occurred.
6.3.3
When BOREN<1:0> = 10, BOR remains under hard-
ware control and operates as previously described.
However, whenever the device enters Sleep mode,
BOR is automatically disabled. When the device
returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
6.3.4
Deep Sleep BOR is a very low-power BOR circuitry.
Due to low current consumption, accuracy may vary.
DSBOR occurs anywhere between 1.55V and 1.95V.
DSBOR is selected in configuration through the
BORV<1:0> (FPOR<6:5>) bits = 00.
DSBOR re-arms the POR anywhere between 1.55V
and 1.95V; however, below 1.55V, the POR is asserted.
Note:
DETECTING BOR
Even when the device exits from Deep
Sleep mode, both the POR and BOR are
set.
DISABLING BOR IN SLEEP MODE
DEEP SLEEP BOR (DSBOR)
DS39937B-page 55