AT89LP2052-20SU Atmel, AT89LP2052-20SU Datasheet
AT89LP2052-20SU
Specifications of AT89LP2052-20SU
Related parts for AT89LP2052-20SU
AT89LP2052-20SU Summary of contents
Page 1
... CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forc- ing instructions to execute in 12 clock cycles. In the AT89LP2052/LP4052 CPU, instructions need only clock cycles providing times more through- put than the standard 8051 ...
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... In addition both timer/counters may be configured as 8-bit Pulse Width Modulators with 8-bit prescalers. The I/O ports of the AT89LP2052/LP4052 can be independently configured in one of four oper- ating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tri-stated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down ...
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... MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured I/O as slave, this pin is an output. P1.7: User-configurable I/O Port 1 bit 7. I/O 19 P1.7 SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is I/O an input. 20 VCC I Supply Voltage 3547J–MICRO–10/09 AT89LP2052/LP4052 3 ...
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... Configurable I/O 5. Memory Organization The AT89LP2052/LP4052 uses a Harvard Architecture with separate address spaces for pro- gram and data memory. The program memory has a regular linear address space with support for up to 64K bytes of directly addressable application code. The data memory has 256 bytes of internal RAM which is divided into regions that may be accessed by different instruction classes ...
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... Data Memory The AT89LP2052/LP4052 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory. The lower 128 bytes of data memory may be accessed through both direct and indirect addressing. The upper 128 bytes of data memory and the 128 bytes of I/O memory share the same address space (see be accessed using indirect addressing ...
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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 6-1. AT89LP2052/LP4052 SFR Map and Reset Values 0F8H 0F0H B* ...
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... Comparison to Standard 8051 The AT89LP2052/LP4052 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assign- ments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are differ- ent from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051 ...
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... Enhanced CPU The AT89LP2052/LP4052 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2-mode 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...
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... Single-cycle ALU Operation (Example: INC R0) System Clock Total Execution Time ALU Operation Execute Result Write Back Fetch Next Instruction Two-Cycle ALU Operation (Example: ADD A, System Clock Total Execution Time ALU Operation Execute Result Write Back Fetch Next Instruction AT89LP2052/LP4052 #data ...
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... AT89LP2052 and 4K bytes for the AT89LP4052. This should be the responsi- bility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89LP2052 (with 2K bytes of memory), whereas LJMP 900H would not ...
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... Low Frequency C1 0–10 pF for Crystals = 0–10 pF for Ceramic Resonators R1 = 4–5 MΩ Quartz Crystal Clock Input Frequency (MHz) AT89LP2052/LP4052 Figure 11-1. Either a quartz crystal or Figure 11-2, 11-3, 11-4 and C2 ~ ~10 pF (B) High Frequency C1=C2=0pF C1=C2=5pF C1=C2=10pF 11-5 illustrate ...
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... Figure 11-3. Quartz Crystal Clock Source ( Figure 11-4. Ceramic Resonator Clock Source (A) AT89LP2052/LP4052 12 Quartz Crystal Clock Input Frequency (MHz) Ceramic Resonator Clock Input Frequency (MHz) C2=0pF C2=5pF C2=10pF R1=4 MΩ C1=C2=0pF C1=C2=5pF C1=C2=10pF 3547J–MICRO–10/09 ...
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... Figure 11-5. Ceramic Resonator Clock Source (B) To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 11-6. External Clock Drive Configuration 3547J–MICRO–10/09 Ceramic Resonator Clock Input Frequency (MHz) Figure 11-6. AT89LP2052/LP4052 C2=0pF C2=5pF C2=10pF R1=4 MΩ ...
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... Reset During reset, all I/O Registers are set to their initial values, the port pins are tri-stated, and the program starts execution from the Reset Vector, 0000H. The AT89LP2052/LP4052 has four sources of reset: power-on reset, brown-out reset, external reset, and watchdog reset. ...
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... The RST pin must be held high for longer than the time-out period to ensure that the device is reset properly. The device will begin execut- ing once RST is brought back low. 3547J–MICRO–10/09 AT89LP2052/LP4052 has been reduced. Power-down CC 15 ...
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... Idle Mode bit. Setting this bit activates Idle mode operation 14. Interrupts The AT89LP2052/LP4052 provides 6 interrupt sources: two external interrupts, two timer inter- rupts, a serial port interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. ...
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... In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. 3547J–MICRO–10/09 Interrupt Vector Addresses Source RST or POR or BOD IE0 TF0 IE1 TF1 SPIF – CF AT89LP2052/LP4052 Vector Address 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 17 ...
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... Thus single-interrupt system, the response time is always more than 5 clock cycles and less than 13 clock cycles. See Figure 14-1. Minimum Interrupt Response Time Figure 14-2. Maximum Interrupt Response Time AT89LP2052/LP4052 18 Figures 14-1 and 14-2. Clock Cycles ...
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... Timer 1 Interrupt Priority Low PX1 External Interrupt 1 Priority Low PT0 Timer 0 Interrupt Priority Low PX0 External Interrupt 0 Priority Low 3547J–MICRO–10/09 – ES ET1 – PS PT1 AT89LP2052/LP4052 Reset Value = 00X0 0000B EX1 ET0 EX0 Reset Value = X0X0 0000B PX1 PT0 PX0 ...
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... PX0H External Interrupt 0 Priority High 15. I/O Ports All 15 port pins on the AT89LP2052/LP4052 may be configured to one of four modes: quasi-bidi- rectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may be assigned in software on a pin-by-pin basis as shown in default to input-only mode after reset. Each port pin also has a Schmitt-triggered input for improved input noise rejection ...
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... Figure 15-3. Input Only for P3.2 and P3.3 3547J–MICRO–10/09 1 Clock Delay (D Flip-Flop) From Port Register Input Data Figure 15- Schmitt-triggered input for improved Input Data PWD Input Data AT89LP2052/LP4052 Figure 15-1. The input Figure 15-3 Very Strong Weak Weak Port ...
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... Port 1 Analog Functions The AT89LP2052/LP4052 incorporates an analog comparator. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled. Digital outputs are disabled by put- ting the port pins into the input-only mode as described in Digital inputs on P1 ...
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... SETB PX.Y 15.7 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP2052/LP4052 share functionality with the various I/Os needed for the peripheral units. pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, oth- erwise, the input/output will always be “ ...
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... P3.5 P3.6 16. Enhanced Timer/Counters The AT89LP2052/LP4052 has two 16-bit Timer/Counter registers: Timer 0 and Timer Timer, the register is incremented every clock cycle. Thus, the register counts clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. ...
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... Control TR1 GATE Figure Figure 16-2. The reload registers default to 0000H, which gives OSC C C Pin Control TR1 GATE AT89LP2052/LP4052 TL1 (8 Bits) PSC1 TH1 TF1 (8 Bits) 16-1. There are two different GATE bits, one for RL1 RH1 (8 Bits) (8 Bits) Reload TL1 ...
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... Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP2052/LP4052 can appear to have three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
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... The flag will be set or cleared by hardware depending on the state of P3.2. IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. 3547J–MICRO–10/09 TF0 TR0 IE1 AT89LP2052/LP4052 Reset Value = 0000 0000B IT1 IE0 IT0 ...
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... Timer SFR TCON TMOD TL0 TL1 TH0 TH1 TCONB RL0 RL1 RH0 RH1 AT89LP2052/LP4052 GATE Mode Operating Mode 0 Variable 9 - 16-bit Timer/Counter. 8-bit Timer/Counter THz with TLx 8-bit prescaler. 1 16-bit Auto Reload Timer/Counter. 8-bit Timer/Counters THx and TLx are cascaded; there is no prescaler. ...
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... Figure 16-5. Asymmetrical Pulse Width Modulation 3547J–MICRO–10/09 PSC12 PSC11 PSC10 Figure 16-6). The PSC0 bits in TCONB control the prescaler AT89LP2052/LP4052 Reset Value = 0010 0100B PSC02 PSC01 PSC00 Figure 16-5 for PWM waveform Counter Value (TH0) Compare Value (RH0) ...
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... The INT0 and INT1 external interrupt sources can be programmed to be level-activated or tran- sition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is nega- tive edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle AT89LP2052/LP4052 30 OSC Control ...
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... The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. The following example shows how to use the serial interrupt for multiprocessor communications. When the master processor must transmit a block of data to one of several slaves, it first sends 3547J–MICRO–10/09 AT89LP2052/LP4052 31 ...
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... Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the RI other modes, in any serial reception (except see SM2). Must be cleared by software. Notes: 1. SMOD0 is located at PCON. oscillator frequency. osc AT89LP2052/LP4052 32 SM2 REN TB8 ...
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... Mode 0 Baud Rate = ------------------------------------------------------ - SMOD1 2 × ------------------- - Mode 2 Baud Rate (Oscillator Frequency SMOD1 2 Modes 1, 3 × ------------------- - = (Timer 1 Overflow Rate) Baud Rate 32 SMOD1 Modes Oscillator Frequency × ------------------- - ------------------------------------------------------ - = [ Baud Rate 32 SMOD1 2 Oscillator Frequency Modes 1, 3 × ------------------- - -------------------------------------------------------- - = [ Baud Rate 32 65536 AT89LP2052/LP4052 256 TH1 – – RH1,RL1 33 ...
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... RX Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set. AT89LP2052/LP4052 34 lists commonly used baud rates and how they can be obtained from Timer 1. ...
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... Figure 18-1. Serial Port Mode 0 1/2 f osc WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) 3547J–MICRO–10/09 INTERNAL BUS “1“ INTERNAL BUS AT89LP2052/LP4052 35 ...
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... Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP2052/LP4052, the baud rate is determined by the Timer 1 overflow rate. The baud rate is determined by the Timer 1 overflow rate. ...
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... ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP2052/LP4052 TXD SHIFT D6 D7 STOP BIT STOP BIT 37 ...
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... SBUF. One bit time later, whether the above conditions were met or not, the unit continues looking for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. AT89LP2052/LP4052 38 show a functional diagram of the serial port in Modes 2 and 3. The ...
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... Figure 18-3. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3547J–MICRO–10/09 AT89LP2052/LP4052 INTERNAL BUS INTERNAL BUS 39 ...
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... CLOCK WRITE TO SBUF SEND DATA SHIFT D0 D1 TXD START BIT TI STOP BIT GEN RX ÷16 RESET CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP2052/LP4052 40 INTERNAL BUS TB8 SBUF CL ZERO DETECTOR STOP BIT SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI SERIAL PORT ÷ ...
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... Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. 3547J–MICRO–10/09 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X AT89LP2052/LP4052 41 ...
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... UART drivers which do not make use of this feature. 19. Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89LP2052/LP4052 and peripheral devices or between multiple AT89LP2052/LP4052 devices. The AT89LP2052/LP4052 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • ...
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... SPI Clock Generator Oscillator MSB Divider ÷4÷8÷32÷64 SPI Clock (Mater) Select MSTR SPE SPI Control 8 SPI Status Register 8 SPI Interrupt Internal Request Data Bus AT89LP2052/LP4052 Figure MSB Slave MISO MISO 8-Bit Shift Register MOSI MOSI SCK SCK LSB ...
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... WCOL, and continues trans- mission without stopping and restarting the clock generator. As long as the CPU can keep the write buffer full in this manner, multiple bytes may be transferred with minimal latency between bytes. AT89LP2052/LP4052 44 3547J–MICRO–10/09 ...
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... Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE. 2. Enable the master SPI prior to the slave device. 3. Slave echoes master on the next Tx if not loaded with new data. 3547J–MICRO–10/09 DORD MSTR CPOL AT89LP2052/LP4052 Reset Value = 0000 0000B CPHA SPR1 SPR0 follows: OSC. ...
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... When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the SPDR register. Table 19-3. SPDR – SPI Data Register SPDR Address = 86H Not Bit Addressable SPD7 SPD6 Bit 7 6 AT89LP2052/LP4052 46 LDEN – – SPD5 SPD4 SPD3 ...
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... Serial Master 8 2 MUX LATCH CLK 8 Parallel Master (Write Buffer LATCH CLK and 19-5. To prevent glitches on SCK from disrupting the interface, CPHA, AT89LP2052/LP4052 Serial Slave 2 MUX Serial Out LATCH CLK Parallel Slave (Read Buffer) Receive Byte LATCH CLK ...
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... P1.7, P1.6 and P1.4 set to “1”. MISO should be set as bidirec- tional or output, with P1.6 set to “1”. If all four pins are set as bidirectional and their respectively port bits are all “1” possible to switch between Master and Slave mode without reconfiguring the pins. AT89LP2052/LP4052 ...
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... Analog Comparator A single analog comparator is provided on the AT89LP2052/LP4052. Comparator operation is such that the output is a logic “1” when the positive input AIN0 (P1.0) is greater than the negative input AIN1 (P1.1). Otherwise, the output is a zero. Setting the CEN bit in ACSR enables the comparator. When the comparator is first enabled, the comparator output and interrupt flag are guaranteed to be stable only after 10 µ ...
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... CM [2:0] Comparator Interrupt Mode Interrupt Mode Negative (Low) level Positive edge Toggle with debounce Positive edge with debounce Negative edge Toggle Negative edge with debounce Positive (High) level AT89LP2052/LP4052 50 CIDL CF CEN Reset Value = XXX0 0000B CM2 CM1 CM0 3547J–MICRO–10/09 ...
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... Watchdog Timer Time-out Period Selection WDT Prescaler Bits PS2 PS1 *The WDT time-out period is dependent on the system clock frequency. MOV WDTRST, #01Eh MOV WDTRST, #0E1h AT89LP2052/LP4052 Period* PS0 (Clock Cycles) 0 16K 1 32K 0 64K 1 128K 0 256K 1 512K 0 1024K 1 2048K Table 21-1 for 51 ...
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... The AT89LP2052/LP4052 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP2052/LP4052 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP2052/LP4052 may take clock cycles to complete. The execution times of most instructions may be computed using Table 22-1 ...
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... SUBB A, @Ri SUBB A, #data INC Rn INC direct INC @Ri INC A DEC Rn DEC direct DEC @Ri DEC A INC DPTR MUL AB DIV 3547J–MICRO–10/09 Generic Instruction Execution Times and Exceptions Detailed Arithmetic Instruction Summary Bytes AT89LP2052/LP4052 Cycle Count # bytes # bytes + 1 Clock Cycles 8051 LP2052 ...
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... ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A SWAP A AT89LP2052/LP4052 54 Detailed Logical Instruction Summary Bytes Clock Cycles 8051 LP2052 ...
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... MOVC A, @A+PC PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Table 22-5. Bit Instruction CLR C CLR bit SETB C 3547J–MICRO–10/09 Detailed Data Transfer Instruction Summary Bytes Detailed Bit Instruction Summary Bytes AT89LP2052/LP4052 Clock Cycles 8051 LP2052 ...
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... RETI AJMP addr11 LJMP addr16 JMP @A+DPTR CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP AT89LP2052/LP4052 56 Detailed Bit Instruction Summary Bytes Detailed Branching Instruction Summary Bytes Clock Cycles 8051 LP2052 2 12 ...
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... Device # AT89LP2052 AT89LP4052 The AT89LP2052/LP4052 provides two flexible interfaces for programming the Flash memory: a parallel interface which uses 10 pins; and a serial interface which uses the 4 SPI pins. The par- allel and serial programming algorithms are identical. Both interfaces support the same command format where each command is issued to the device one byte at a time ...
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... Bit 3 System Clock Out *The AT89LP2052/LP4052 has ISP enabled by default from the factory. However, if ISP is later disabled, the ISP Enable Fuse must be enabled by using Parallel Programming before entering ISP mode. When disabling the ISP fuse during ISP, the current ISP session will remain active until RST is brought low. ...
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... DATA Polling The AT89LP2052/LP4052 implements DATA polling to indicate the end of a programming cycle. While the device is busy, any attempted read of the last byte written will return the data byte with the MSB complemented. Once the programming cycle has completed, the true value will be accessible ...
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... CS XTAL1 P1 Figure 23-4. Parallel Read Command Sequence CS XTAL1 P1 AT89LP2052/LP4052 60 AT89LP2052/LP4052 R DY/BSY P3.1 CS P3.2 X TAL 1 GND Sampling of pin P3.1 (RDY/BSY) is optional. During Parallel Programming, P3.1 will be pulled low while the device is busy. Note that it does not require an external passive pull- Figure 23-4 shows a generic parallel read command sequence ...
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... RST to “H” 12V to enable the parallel programming modes. PP has settled, wait an additional 10 µs before programming RST P3.2 XTAL1 P1 down from 12V RST P3.2 XTAL1 P1 The waveforms on this page are not to scale. AT89LP2052/LP4052 HIGH Z and wait 10 µs. HIGH ...
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... Lockbit1 and Lockbit2 are programmed to “unlock” state. Usage: 1. Bring CS (P3.2) low. 2. Drive P1 to AAh and pulse XTAL1 high. 3. Drive P1 to 8Ah and pulse XTAL1 high. 4. Bring CS high. 5. Wait 4 ms, monitor P3.1, or poll data/status. Figure 23-8. Chip Erase Sequence RDY/BSY Note: AT89LP2052/LP4052 AAh ACh CS XTAL1 ...
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... Bytes should not be loaded more than once. 7. Bring CS high. Figure 23-9. Load Page Buffer Sequence CS XTAL1 Note: 3547J–MICRO–10/09 P1 AAh 51h The waveform on this page is not to scale. AT89LP2052/LP4052 00h 000bbbbb DIN 0 DIN 1 DIN n 63 ...
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... Note: Figure 23-10. Write Code Page Sequence CS XTAL1 P1 RDY/BSY Note: AT89LP2052/LP4052 not possible to skip bytes while loading data during write. To load non-contiguous bytes in a page, use the Load Page Buffer command. AAh 50h 0000aaaa aaabbbbb The waveform on this page is not to scale. ...
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... To read additional data bytes in the page, pulse XTAL1 high to increment to the next address. 10. Drive CS high. Figure 23-11. Read Code Page Sequence CS XTAL1 Note: 3547J–MICRO–10/09 P1 AAh 30h 0000aaaa aaabbbbb The waveform on this page is not to scale. AT89LP2052/LP4052 DOUT 0 DOUT 1 DOUTn 65 ...
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... Note: Figure 23-12. Write User Signature Page Sequence CS XTAL1 P1 RDY/BSY Note: AT89LP2052/LP4052 not possible to skip bytes while loading data during write. To load non-contiguous bytes in a page, use the Load Page Buffer command. AAh 52h 00h The waveform on this page is not to scale. ...
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... To read additional data bytes in the page, pulse XTAL1 high to increment to the next address. 10. Drive CS high. Figure 23-13. Read User Signature Page Sequence CS XTAL1 Note: 3547J–MICRO–10/09 P1 AAh 32h The waveform on this page is not to scale. AT89LP2052/LP4052 00h 000bbbbb DOUT 0 DOUT 1 DOUTn 67 ...
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... Read data from P1 read additional data bytes in the page, pulse XTAL1 high to increment to the next address. 10. Drive CS high. Figure 23-14. Read Atmel Signature Page Sequence CS XTAL1 P1 Note: AT89LP2052/LP4052 68 AAh 38h 00h The waveform on this page is not to scale. 000bbbbb DOUT 0 DOUT 1 DOUTn ...
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... Tri-state P1. 7. Bring XTAL1 low. 8. Read data from P1. 9. Drive CS high. Figure 23-16. Read Lock Bits Sequence XTAL1 Note: 3547J–MICRO–10/ AAh E4h 00h CS P1 AAh 64h The waveforms on this page are not to scale. AT89LP2052/LP4052 00h 111111LL 00h 00h 111111LL 69 ...
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... Drive P1 to 0x00 and pulse XTAL1 high. 5. Drive P1 to 0x00 and bring XTAL1 high. 6. Tri-state P1. 7. Bring XTAL1 low. 8. Read data from P1. 9. Drive CS high. Figure 23-18. Read User Fuses Sequence XTAL1 Note: AT89LP2052/LP4052 70 P1 AAh E1h 00h CS P1 AAh 61h The waveforms on this page are not to scale ...
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... Drive P1 to 0x00 and pulse XTAL1 high. 5. Drive P1 to 0x00 and bring XTAL1 high. 6. Tri-state P1. 7. Bring XTAL1 low. 8. Read data from P1. 9. Drive CS high. Figure 23-19. Read Status Sequence XTAL1 Note: 3547J–MICRO–10/ AAh 60h The waveform on this page is not to scale. AT89LP2052/LP4052 00h 00h 1111SSSS 71 ...
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... Figure 23-20. Flash Programming and Verification Waveforms in Parallel Mode AT89LP2052/LP4052 72 3547J–MICRO–10/09 ...
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... PWRDN 23.5 In-System Programming (ISP) The AT89LP2052/LP4052 offers a serial programming interface which may be used in place of the parallel programming interface or to program the device while in system. In this document serial programming and In-System Programming (ISP) refer to the same interface. ISP supports the same command set as parallel programming. However, during ISP command bytes are entered serially over the Serial Peripheral Interface (SPI) pins ...
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... Keep SCK (P1.7) and SS (P1.4) at “L”. 3. Wait 10 µs and bring RST and SS to “H”. 4. Wait at least 2 ms for internal Power-on Reset to time out. Figure 23-22. Serial Programming Power-up Sequence AT89LP2052/LP4052 74 AT89LP2052/LP4052 Serial Clock P1.7/SCK Serial Out P1.6/MISO Se rial In P1.5/MOSI CS P1 ...
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... Bring RST to “H”. 4. Bring SCK (P1.7) to “L”. Figure 23-24. In-System Programming (ISP) Start Sequence 3547J–MICRO–10/ RST SS SCK MISO MOSI The waveforms on this page are not to scale XTAL1 RST SS SCK MISO MOSI AT89LP2052/LP4052 HIGH Z HIGH Z HIGH Z HIGH Z 75 ...
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... Figure 23-25. In-System Programming (ISP) Exit Sequence Note: 23.5.5 ISP Byte Sequence The ISP byte sequence is shown in • Data shifts in/out MSB first. • MISO changes at falling edge of SCK. • MOSI is sampled at rising edge of SCK. Figure 23-26. ISP Byte Sequence AT89LP2052/LP4052 XTAL1 RST SS SCK MISO MOSI The waveforms on this page are not to scale ...
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... SOX t SS Enable Lead Time SSE t SS Disable Lag Time SSD t Wire Cycle Time WRC t Erase Cycle Time ERS 3547J–MICRO–10/ Opcode Address High X X Min 200 100 100 100 AT89LP2052/LP4052 Figure 23-27 Address Low Data Data Out Max Units ...
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... Figure 23-28. Serial Programming Interface Timing SS SCK MISO MOSI 24. Electrical Characteristics 24.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +6.2V Maximum Operating Voltage ............................................ 5.5V DC Output Current...................................................... 15.0 mA AT89LP2052/LP4052 SCK SSE t t SHSL SLSH t ...
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... < V < Test Freq MHz, T Active Mode, 12 MHz, V Idle Mode, 12 MHz 5. must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89LP2052/LP4052 Min -0.5 -0 85°C A 2 25° 5.5V/ 5.5V/3V CC ...
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... Serial Input Hold Time SIH t Serial Output Hold Time SOH t Serial Output Valid Time SOV t Output Enable Time SOE t Output Disable Time SOX t Slave Enable Lead Time SSE t Slave Disable Lag Time SSD AT89LP2052/LP4052 80 Min Max 41.6 4t CLCL SCK SCK Min Max 41 ...
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... SCK (CPOL = 1) MISO MOSI 3547J–MICRO–10/ SCK t t SHSL SLSH t t SLSH SHSL t t SOH SOV SCK SSE t t SHSL SLSH t t SLSH SHSL SOV SOH SOE t SF AT89LP2052/LP4052 SIS SIH t t SSD SF t SOX t t SIS SIH SOV 81 ...
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... Figure 24-5. External Clock Drive Waveform Table 24-3. External Clock Drive Parameters Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89LP2052/LP4052 2.4V to 5.5V CC Min Max Units MHz 3547J–MICRO–10/09 ...
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... Load Capacitance = 80 pF VALID VALID VALID (1) - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at CC max. for a logic “0” level occurs AT89LP2052/LP4052 Variable Oscillator Min Max 2t -15 CLCL t -15 CLCL t -15 CLCL ...
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... Test Condition, Active Mode, All Other Pins are Disconnected CC 24.6.4 I Test Condition, Idle Mode, All Other Pins are Disconnected CC 24.6.5 Clock Signal Waveform for 0.5V CC 0.45V 24.6.6 I Test Condition, Power-down Mode, All Other Pins are Disconnected AT89LP2052/LP4052 RST P1, P3 XTAL2 (NC) CLOCK SIGNAL XTAL1 GND V CC RST P1, P3 XTAL2 ...
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... Wide, Plastic Gull Wing Small Outline (SOIC) 20X 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 3547J–MICRO–10/09 Ordering Code Package AT89LP2052-20PU AT89LP2052-20SU AT89LP2052-20XU AT89LP4052-20PU AT89LP4052-20SU AT89LP4052-20XU Package Type AT89LP2052/LP4052 Operation Range 20P3 ...
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... A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LP2052/LP4052 86 D PIN TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual ...
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... SOIC 3547J–MICRO–10/09 AT89LP2052/LP4052 87 ...
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... TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC 0.65 (.0256) BSC 0º ~ 8º 2325 Orchard Parkway San Jose, CA 95131 R AT89LP2052/LP4052 88 PIN 1 4.50 (0.177) 4.30 (0.169) 6.60 (.260) 6.40 (.252) 0.15 (0.006) 0.30 (0.012) 0.05 (0.002) ...
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... Changed TMOD to TCON (Table 16-1 on page Changed SPI = 1 and SPI = 0 to SPE = 1 and SPE = 0 Removed Standard Packaging Offering. Added R1 option to oscillator connection diagram Added related oscillator amplitude graphs AT89LP2052/LP4052 was inserted. 46, the Divider ratios were changed (page 50) 58, several changes were = 2 ...
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... AT89LP2052/LP4052 90 3547J–MICRO–10/09 ...
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... Interrupt Handling ..................................................................................................7 7.4 Timer/Counters ......................................................................................................7 7.5 Serial Port ..............................................................................................................7 7.6 Watchdog Timer ....................................................................................................7 7.7 I/O Ports ................................................................................................................8 7.8 Reset .....................................................................................................................8 9.1 Branching Instructions .........................................................................................10 9.2 MOVX-related Instructions, Data Memory ...........................................................10 10.1 Crystal Oscillator .................................................................................................10 10.2 External Clock Source .........................................................................................10 10.3 System Clock Out ................................................................................................10 12.1 Power-on Reset ...................................................................................................14 12.2 Brown-out Reset ..................................................................................................14 AT89LP2052/LP4052 i ...
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... Table of Contents (Continued) 13. Power Saving Modes ............................................................................. 14 14. Interrupts ................................................................................................ 16 15. I/O Ports .................................................................................................. 20 16. Enhanced Timer/Counters .................................................................... 24 17. External Interrupts ................................................................................. 30 18. Serial Interface ....................................................................................... 31 AT89LP2052/LP4052 ii 12.3 External Reset .....................................................................................................14 12.4 Watchdog Reset ..................................................................................................14 13.1 Idle Mode .............................................................................................................15 13.2 Power-down Mode ..............................................................................................15 14.1 Interrupt Response Time .....................................................................................17 15.1 Quasi-bidirectional Output ...................................................................................20 15.2 Input-only Mode ...................................................................................................21 15 ...
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... Absolute Maximum Ratings* ...............................................................................78 24.2 DC Characteristics ..............................................................................................79 24.3 Serial Peripheral Interface Timing ......................................................................80 24.4 External Clock Drive ............................................................................................82 24.5 Serial Port Timing: Shift Register Mode ..............................................................83 24.6 Test Conditions ...................................................................................................83 25.1 Green Package Option (Pb/Halide-free) .............................................................85 26.1 20P3 – PDIP ........................................................................................................86 26.2 20S2 – SOIC ......................................................................................................87 26.3 20X – TSSOP ......................................................................................................88 AT89LP2052/LP4052 iii ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...