AT89LP2052-20SU Atmel, AT89LP2052-20SU Datasheet - Page 4
![IC 8051 MCU FLASH 2K 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
AT89LP2052-20SU
Manufacturer Part Number
AT89LP2052-20SU
Description
IC 8051 MCU FLASH 2K 20SOIC
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP2052-20PU.pdf
(94 pages)
Specifications of AT89LP2052-20SU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Package
20SOIC W
Device Core
8051
Family Name
AT89
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
4. Block Diagram
5. Memory Organization
5.1
4
Program Memory
AT89LP2052/LP4052
The AT89LP2052/LP4052 uses a Harvard Architecture with separate address spaces for pro-
gram and data memory. The program memory has a regular linear address space with support
for up to 64K bytes of directly addressable application code. The data memory has 256 bytes of
internal RAM which is divided into regions that may be accessed by different instruction classes.
The AT89LP2052/LP4052 does not support external RAM.
The AT89LP2052/LP4052 contains 2/4K bytes of on-chip In-System Programmable Flash mem-
ory for program storage. The Flash memory has an endurance of at least 10,000 write/erase
cycles.
on Flash Programming in ISP or Parallel Programming mode. The reset and interrupt vectors
are located within the first 59 bytes of program memory (see
16). Constant tables can be allocated within the entire 2/4-Kbyte program memory address
space for access by the MOVC instruction.
Configurable I/O
Configurable I/O
Single Cycle
Section 23. “Programming the Flash Memory” on page 57
8051 CPU
2/4-Kbyte
256-Byte
Flash
Port 3
Port 1
RAM
CPU Clock
Configurable
Comparator
Watchdog
Oscillator
Timer 0
Timer 1
Analog
UART
Timer
SPI
Section 14. “Interrupts” on page
contains a detailed description
Resonator
Crystal or
3547J–MICRO–10/09