AT89LP2052-20SU Atmel, AT89LP2052-20SU Datasheet - Page 32
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AT89LP2052-20SU
Manufacturer Part Number
AT89LP2052-20SU
Description
IC 8051 MCU FLASH 2K 20SOIC
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP2052-20PU.pdf
(94 pages)
Specifications of AT89LP2052-20SU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Package
20SOIC W
Device Core
8051
Family Name
AT89
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Table 18-1.
Notes:
32
SCON Address = 98H
Bit Addressable
Bit
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
(SMOD0 = 0/1)
1. SMOD0 is located at PCON.6.
2. f
AT89LP2052/LP4052
SM0/FE
osc
Function
Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set
regardless of the state of SMOD0.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode
0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the
other modes, in any serial reception (except see SM2). Must be cleared by software.
7
SCON – Serial Port Control Register
= oscillator frequency.
SM0
0
0
1
1
(1)
out an address byte that identifies the target slave. An address byte differs from a data byte in
that the 9th bit is “1” in an address byte and “0” in a data byte. With SM2 = 1, no slave is inter-
rupted by a data byte. An address byte, however, interrupts all slaves, so that each slave can
examine the received byte and see if it is being addressed. The addressed slave clears its SM2
bit and prepares to receive the data bytes that follows. The slaves that are not addressed set
their SM2 bits and ignore the data bytes.
The SM2 bit has no effect in Mode 0 but can be used to check the validity of the stop bit in
Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid
stop bit is received.
SM1
6
SM1
0
1
0
1
SM2
5
Mode
0
1
2
3
REN
4
Description
shift register
8-bit UART
9-bit UART
9-bit UART
TB8
3
RB8
f
osc
Baud Rate
2
/32 or f
variable
variable
f
osc
/2
osc
(2)
Reset Value = 0000 0000B
/16
T1
1
3547J–MICRO–10/09
RI
0