AT89LP2052-20SU Atmel, AT89LP2052-20SU Datasheet - Page 27
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AT89LP2052-20SU
Manufacturer Part Number
AT89LP2052-20SU
Description
IC 8051 MCU FLASH 2K 20SOIC
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP2052-20PU.pdf
(94 pages)
Specifications of AT89LP2052-20SU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Package
20SOIC W
Device Core
8051
Family Name
AT89
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Table 16-1.
3547J–MICRO–10/09
Bit
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON = 88H
Bit Addressable
TF1
Function
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to
interrupt routine.
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to
interrupt routine.
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.
Interrupt 1 flag. When IT1 is set, IE1 is set by hardware when the external interrupt falling edge is detected, and is cleared
by hardware when the CPU vectors to the interrupt routine. When IT1 is cleared, IE1 is sampled and inverted from the
external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.3.
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
Interrupt 0 flag. When IT0 is set, IE0 is set by hardware when the external interrupt falling edge is detected, and is cleared
by hardware when the CPU vectors to the interrupt routine. When IT0 is cleared, IE0 is sampled and inverted from the
external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.2.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
7
TCON
– Timer/Counter Control Register
TR1
6
TF0
5
TR0
4
IE1
3
IT1
2
AT89LP2052/LP4052
Reset Value = 0000 0000B
IE0
1
IT0
0
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