PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 215

IC PIC MCU FLASH 4KX16 64TQFP

PIC18F6310-I/PT

Manufacturer Part Number
PIC18F6310-I/PT
Description
IC PIC MCU FLASH 4KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F6310-I/PT

Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI/I2C/EUSART/AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F6310-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
17.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 17-31:
FIGURE 17-32:
 2010 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SDA
SCL
PEN
BCLIF
P
SSPIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
PIC18F6310/6410/8310/8410
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
(Figure
17-31). If the SCL pin is
(Figure
SDA sampled
low after T
set BCLIF
‘0’
‘0’
DS39635C-page 215
‘0’
‘0’
17-32).
BRG
,

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