PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 97

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When the device is executing out of internal memory
(EBDIS = 0) in Microprocessor with Boot Block mode or
Extended Microcontroller mode, the control signals will
NOT be active. They will go to a state where the
AD<15:0> and A<19:16> are tri-state; the CE, OE, WRH,
WRL, UB and LB signals are ‘1’; ALE and BA0 are ‘0’.
Note that only those pins associated with the current
address width are forced to tri-state; the other pins con-
tinue to function as I/O. In the case of a 16-bit address
width, for example, only AD<15:0> (PORTD and
PORTE) are affected; A<19:16> (PORTH<3:0>) con-
tinue to function as I/O. In all external memory modes,
the bus takes priority over any other peripherals that
may share pins with it. This includes the Parallel Slave
Port and serial communications modules which would
otherwise take priorityover the I/O port.
8.2
In 16-bit mode, the external memory interface can be
connected to external memories in three different
configurations:
• 16-Bit Byte Write
• 16-Bit Word Write
• 16-Bit Byte Select
The configuration to be used is determined by the
WM<1:0>
(MEMCON<1:0>). These three different configurations
allow the designer maximum flexibility in using both
8-bit and 16-bit devices with 16-bit data.
FIGURE 8-1:
 2010 Microchip Technology Inc.
Note 1: This signal only applies to table writes. See
PIC18F8410
16-Bit Mode
bits
AD<15:8>
A<19:16>
AD<7:0>
WRH
WRL
ALE
CE
OE
in
16-BIT BYTE WRITE MODE EXAMPLE
the
MEMCON
PIC18F6310/6410/8310/8410
register
373
373
Section 7.1 “Table Reads and Table
D<7:0>
A<19:0>
D<15:8>
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits, A<15:0>, are avail-
able on the external memory interface bus. Following the
address latch, the Output Enable signal (OE) will enable
both bytes of program memory at once to form a 16-bit
instruction word. The Chip Enable signal (CE) is active
at any time that the microcontroller accesses external
memory, whether reading or writing; it is inactive
(asserted high) whenever the device is in Sleep mode.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O line
to select between Byte and Word mode. The other 16-bit
modes do not need BA0. JEDEC standard static RAM
memories will use the UB or LB signals for byte selection.
8.2.1
Figure 8-1
mode for PIC18F8310/8410 devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD<15:0> bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
shows an example of 16-Bit Byte Write
16-BIT BYTE WRITE MODE
A<x:0>
D<7:0>
CE
OE
(MSB)
WR
(1)
Writes”.
Address Bus
Data Bus
Control Lines
D<7:0>
DS39635C-page 97
A<x:0>
D<7:0>
CE
OE
(LSB)
WR
(1)