PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 339

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.2
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F6310/6410/8310/8410 devices
also provide an optional extension to the core CPU
functionality. The added features include eight addi-
tional instructions that augment Indirect and Indexed
Addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set can all be classi-
fied as literal operations which either manipulate the
File Select Registers, or use them for Indexed Address-
ing. Two of the instructions, ADDFSR and SUBFSR, each
have an additional special instantiation for using FSR2.
These versions (ADDULNK and SUBULNK) allow for
automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and de-allocation of software
• Function Pointer invocation
• Software Stack Pointer manipulation
• manipulation of variables located in a software
TABLE 25-3:
 2010 Microchip Technology Inc.
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
stack space when entering and leaving
subroutines
stack
Note:
Mnemonic,
Operands
Extended Instruction Set
All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use
in symbolic addressing. If a label is used, the instruction syntax then becomes:
{label}
f, k
k
z
z
k
f, k
k
s
s
, f
, z
d
EXTENSIONS TO THE PIC18 INSTRUCTION SET
d
instruction
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
Move z
Move z
Store Literal at FSR2, Decrement FSR2
Subtract Literal from FSR
Subtract Literal from FSR2 and Return
f
z
d
s
s
d
(destination) 2nd word
(source) to
(source) to
(destination) 2nd word
argument(s)
Description
1st word
1st word
PIC18F6310/6410/8310/8410
A summary of the instructions in the extended instruc-
tion set is provided in
are provided in
Set”. The opcode field descriptions in
(page 298) apply to both the standard and extended
PIC18 instruction sets.
25.2.1
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM Assembler will flag
an error if it determines that an index or offset value is
not bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see
Syntax with Standard PIC18
Cycles
Note:
Note:
1
2
2
2
2
1
1
2
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
MSb
16-Bit Instruction Word
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
EXTENDED INSTRUCTION SYNTAX
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text
arguments are denoted by braces (“{ }”).
Section 25.2.3.1 “Extended Instruction
Section 25.2.2 “Extended Instruction
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
and
Table
going
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
ffkk
11kk
0001
25-3. Detailed descriptions
Commands”.
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
forward,
LSb
DS39635C-page 339
Affected
Table 25-1
Status
None
None
None
None
None
None
None
None
optional