DSPIC30F3013-20I/SO Microchip Technology, DSPIC30F3013-20I/SO Datasheet - Page 115

• Manufacturer Part Number: DSPIC30F3013-20I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301320ISO

The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
16.7.1
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 16-1.
• Connect external V
• Set SSRC<2.0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Write the SMPI<3.0> control bits in the ADCON2
• Configure the ADC clock period to be:
• Configure the sampling time to be 1 T
FIGURE 16-3:
© 2008 Microchip Technology Inc.
the recommended circuit shown in Figure 16-2.
enable the auto convert option.
control bit in the ADCON1 register.
register for the desired number of conversions
between interrupts.
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
writing: SAMC<4:0> = 00001.
(14 + 1) x 200,000
200 KSPS CONFIGURATION
GUIDELINE
Note: C
1
Legend: C
VA
PIN
REF
Rs
12-BIT A/D CONVERTER ANALOG INPUT MODEL
value depends on device package and is not tested. Effect of C
+ and V
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
C
= 334 ns
PIN
REF
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
- pins following
dsPIC30F2011/2012/3012/3013
AD
V
by
DD
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
± 500 nA
IC
≤ 250Ω
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
conjunction with the guidelines described above allows
a conversion speed of 200 ksps. See Example 16-1 for
code example.
16.8
The analog input model of the 12-bit ADC is shown in
Figure 16-3. The total sampling time for the A/D is a
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the ADC, the
maximum recommended source impedance, R
is 2.5 kΩ. After the analog input channel is selected
(changed), this sampling function must be completed
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
SS
) impedance combine to directly affect the time
Sampling
Switch
A/D Acquisition Requirements
impedance
R
SS
IC
PIN
) and the internal sampling switch
R
negligible if Rs ≤ 2.5 kΩ.
SS
V
SS
HOLD
C
= DAC capacitance
= 18 pF
≤ 3 kΩ
HOLD
(R
) must be allowed to fully
S
),
HOLD
the
DS70139F-page 115
AD
. The combined
selection in
interconnect
S
,