ATMEGA32A-AU Atmel, ATMEGA32A-AU Datasheet - Page 66
![MCU AVR 32K FLASH 16MHZ 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32A-AU
Manufacturer Part Number
ATMEGA32A-AU
Description
MCU AVR 32K FLASH 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
1024 B
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
10 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32A-AU
Manufacturer:
ATMEL
Quantity:
5 600
Part Number:
ATMEGA32A-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA32A-AUR
Manufacturer:
SMD
Quantity:
5
- Current page: 66 of 353
- Download datasheet (6Mb)
12.4
12.4.1
12.4.2
12.4.3
12.4.4
8155C–AVR–02/11
Register Description
SFIOR – Special Function I/O Register
PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins Address
Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0
• Bit 2 – PUD: Pull-up disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 51
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
ADTS2
PORTA7
PINA7
R/W
DDA7
R/W
R/W
N/A
7
0
R
7
0
7
0
7
PD3/INT1
0
0
0
0
0
0
INT1 ENABLE
1
INT1 INPUT
–
PORTA6
ADTS1
PINA6
DDA6
R/W
R/W
R/W
N/A
R
6
0
6
0
6
6
0
for more details about this feature.
PORTA5
PINA5
DDA5
ADTS0
R/W
R/W
N/A
R/W
5
0
R
5
0
5
5
0
PD2/INT0
0
0
0
0
0
0
INT0 ENABLE
1
INT0 INPUT
–
PORTA4
PINA4
DDA4
R/W
R/W
N/A
4
0
R
4
0
4
R
4
–
0
PORTA3
PINA3
DDA3
R/W
R/W
N/A
ACME
3
0
R
3
0
3
R/W
3
0
PORTA2
PD1/TXD
TXEN
0
TXEN
1
TXEN
TXD
0
0
–
–
PINA2
DDA2
R/W
R/W
N/A
2
0
R
PUD
2
0
2
R/W
2
0
PORTA1
PINA1
DDA1
R/W
R/W
PSR2
N/A
R/W
1
0
R
1
0
1
ATmega32A
1
0
PD0/RXD
0
0
0
0
RXEN
PORTD0 • PUD
RXEN
0
RXD
–
PORTA0
PSR10
PINA0
DDA0
R/W
R/W
R/W
N/A
0
0
R
0
0
0
0
0
SFIOR
PORTA
DDRA
PINA
“Con-
66
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