PIC24FJ64GB002-I/SP Microchip Technology, PIC24FJ64GB002-I/SP Datasheet - Page 202
![IC MCU 16BIT 64KB FLASH 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC24FJ64GB002-I/SP
Manufacturer Part Number
PIC24FJ64GB002-I/SP
Description
IC MCU 16BIT 64KB FLASH 28DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MCP73831T-2DCIOT.pdf
(28 pages)
2.PIC24FJ32GA102-ISP.pdf
(48 pages)
3.PIC24FJ32GB002-ISO.pdf
(352 pages)
4.PIC24FJ32GB002-ISO.pdf
(12 pages)
5.PIC24FJ32GB002-ISO.pdf
(342 pages)
Specifications of PIC24FJ64GB002-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
19
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
19
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, LIN, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MCP73831T-2DCIOT PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GB002-ISO PDF datasheet #3
- PIC24FJ32GB002-ISO PDF datasheet #4
- PIC24FJ32GB002-ISO PDF datasheet #5
- Current page: 202 of 352
- Download datasheet (3Mb)
PIC24FJ64GB004 FAMILY
18.2
Endpoint buffer control is handled through a structure
called the Buffer Descriptor Table (BDT). This provides
a flexible method for users to construct and control
endpoint buffers of various lengths and configurations.
The BDT can be located in any available, 512-byte
aligned block of data RAM. The BDT Pointer
(U1BDTP1) contains the upper address byte of the
BDT, and sets the location of the BDT in RAM. The user
must set this pointer to indicate the table’s location.
The BDT is composed of Buffer Descriptors (BDs)
which are used to define and control the actual buffers
in the USB RAM space. Each BD consists of two, 16-bit
“soft” (non-fixed-address) registers, BDnSTAT and
BDnADR, where n represents one of the 64 possible
BDs (range of 0 to 63). BDnSTAT is the status register
for BDn, while BDnADR specifies the starting address
for the buffer associated with BDn.
FIGURE 18-8:
DS39940D-page 202
Total BDT Space:
Note:
PPB<1:0> = 00
No Ping-Pong
128 bytes
Buffers
USB Buffer Descriptors and the
BDT
Memory area not shown to scale.
EP0 Rx
Descriptor
EP0 Tx
Descriptor
EP1 Rx
Descriptor
EP1 Tx
Descriptor
EP15 Tx
Descriptor
BDT MAPPING FOR ENDPOINT BUFFERING MODES
Ping-Pong Buffer
Total BDT Space:
PPB<1:0> = 01
on EP0 OUT
132 bytes
EP0 Rx Even
Descriptor
EP0 Rx Odd
Descriptor
EP0 Tx
Descriptor
EP1 Rx
Descriptor
EP1 Tx
Descriptor
EP15 Tx
Descriptor
Ping-Pong Buffers
Total BDT Space:
PPB<1:0>0 = 10
on all EPs
256 bytes
indicated by the value of ENDPT3:ENDPT0 in the USB
Depending on the endpoint buffering configuration
used, there are up to 64 sets of buffer descriptors, for a
total of 256 bytes. At a minimum, the BDT must be at
least 8 bytes long. This is because the USB specifica-
tion mandates that every device must have Endpoint 0
with both input and output for initial setup.
Endpoint mapping in the BDT is dependent on three
variables:
• Endpoint number (0 to 15)
• Endpoint direction (Rx or Tx)
• Ping-pong settings (U1CNFG1<1:0>)
Figure 18-8 illustrates how these variables are used to
map endpoints in the BDT.
In Host mode, only Endpoint 0 buffer descriptors are
used. All transfers utilize the Endpoint 0 buffer descriptor
and Endpoint Control register (U1EP0). For received
packets, the attached device’s source endpoint is
status register (U1STAT<7:4>). For transmitted packet,
the attached device’s destination endpoint is indicated
by the value written to the Token register (U1TOK).
EP0 Rx Even
Descriptor
EP0 Rx Odd
Descriptor
EP0 Tx Even
Descriptor
EP0 Tx Odd
Descriptor
EP1 Rx Even
Descriptor
EP1 Rx Odd
Descriptor
EP1 Tx Odd
Descriptor
EP15 Tx Odd
Descriptor
EP1 Tx Even
Descriptor
2010 Microchip Technology Inc.
Ping-Pong Buffers
Total BDT Space:
on all other EPs
PPB<1:0> = 11
except EP0
248 bytes
EP0 Rx
Descriptor
EP0 Tx
Descriptor
EP1 Rx Even
Descriptor
EP1 Rx Odd
Descriptor
EP1 Tx Odd
Descriptor
EP15 Tx Odd
Descriptor
EP1 Tx Even
Descriptor
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