PIC24FJ64GB002-I/SP Microchip Technology, PIC24FJ64GB002-I/SP Datasheet - Page 210
![IC MCU 16BIT 64KB FLASH 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC24FJ64GB002-I/SP
Manufacturer Part Number
PIC24FJ64GB002-I/SP
Description
IC MCU 16BIT 64KB FLASH 28DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MCP73831T-2DCIOT.pdf
(28 pages)
2.PIC24FJ32GA102-ISP.pdf
(48 pages)
3.PIC24FJ32GB002-ISO.pdf
(352 pages)
4.PIC24FJ32GB002-ISO.pdf
(12 pages)
5.PIC24FJ32GB002-ISO.pdf
(342 pages)
Specifications of PIC24FJ64GB002-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
19
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
19
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, LIN, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MCP73831T-2DCIOT PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GB002-ISO PDF datasheet #3
- PIC24FJ32GB002-ISO PDF datasheet #4
- PIC24FJ32GB002-ISO PDF datasheet #5
- Current page: 210 of 352
- Download datasheet (3Mb)
PIC24FJ64GB004 FAMILY
18.5.3
1.
2.
3.
4.
5.
6.
7.
DS39940D-page 210
Note:
Follow the procedure described in Section 18.5.1
“Enable Host Mode and Discover a Connected
Device” and Section 18.5.2 “Complete a Con-
trol Transaction to a Connected Device” to
discover and configure a device.
To enable transmit and receive transfers with
handshaking enabled, write 1Dh to U1EP0. If
the target device is a low-speed device, also set
the LSPD bit (U1EP0<7>). If you want the hard-
ware to automatically retry indefinitely if the
target device asserts a NAK on the transfer,
clear
(U1EP0<6>).
Set up the BD for the current (EVEN or ODD) Tx
EP0 to transfer up to 64 bytes.
Set the USB device address of the target device
in the address register (U1ADDR<6:0>).
Write an OUT token to the desired endpoint to
U1TOK. This triggers the module’s transmit
state machines to begin transmitting the token
and the data.
Wait for the Transfer Done Interrupt Flag,
TRNIF. This indicates that the BD has been
released back to the microprocessor, and the
transfer has completed. If the retry disable bit is
set, the handshake (ACK, NAK, STALL or
ERROR (0Fh)) is returned in the BD PID field. If
a STALL interrupt occurs, the pending packet
must be dequeued and the error condition in the
target device cleared. If a detach interrupt
occurs (SE0 for more than 2.5 s), then the
target has detached (U1IR<0> is set).
Once the transfer done interrupt occurs (TRNIF
is set), the BD can be examined and the next
data packet queued by returning to step 2.
SEND A FULL-SPEED BULK DATA
TRANSFER TO A TARGET DEVICE
the
USB speed, transceiver and pull-ups
should only be configured during the
module setup phase. It is not recom-
mended to change these settings while
the module is enabled.
Retry
Disable
bit,
RETRYDIS
18.6
18.6.1
An OTG A-device may decide to power down the V
supply when it is not using the USB link through the Ses-
sion Request Protocol (SRP). Software may do this by
clearing VBUSON (U1OTGCON<3>). When the V
supply is powered down, the A-device is said to have
ended a USB session.
An OTG A-device or Embedded Host may re-power the
V
OTG B-device may also request that the OTG A-device
re-power the V
is accomplished via Session Request Protocol (SRP).
Prior to requesting a new session, the B-device must
first check that the previous session has definitely
ended. To do this, the B-device must check for two
conditions:
1. V
2. Both D+ and D- have been low for at least 2 ms.
The B-device will be notified of condition 1 by the
SESENDIF (U1OTGIR<2>) interrupt. Software will
have to manually check for condition 2.
The B-device may aid in achieving condition 1 by dis-
charging the V
may do this by setting VBUSDIS (U1OTGCON<0>).
After these initial conditions are met, the B-device may
begin requesting the new session. The B-device begins
by pulsing the D+ data line. Software should do this by
setting DPPULUP (U1OTGCON<7>). The data line
should be held high for 5 to 10 ms.
BUS
Note:
BUS
supply at any time (initiate a new session). An
supply is below the Session Valid voltage, and
OTG Operation
SESSION REQUEST PROTOCOL
(SRP)
When the A-device powers down the V
supply, the B-device must disconnect its
pull-up resistor from power. If the device is
self-powered, it can do this by clearing
DPPULUP
DMPULUP (U1OTGCON<6>).
BUS
BUS
supply (initiate a new session). This
supply through a resistor. Software
2010 Microchip Technology Inc.
(U1OTGCON<7>)
BUS
and
BUS
BUS
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