PIC24FJ64GB002-I/SP Microchip Technology, PIC24FJ64GB002-I/SP Datasheet - Page 345
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PIC24FJ64GB002-I/SP
Manufacturer Part Number
PIC24FJ64GB002-I/SP
Description
IC MCU 16BIT 64KB FLASH 28DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MCP73831T-2DCIOT.pdf
(28 pages)
2.PIC24FJ32GA102-ISP.pdf
(48 pages)
3.PIC24FJ32GB002-ISO.pdf
(352 pages)
4.PIC24FJ32GB002-ISO.pdf
(12 pages)
5.PIC24FJ32GB002-ISO.pdf
(342 pages)
Specifications of PIC24FJ64GB002-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
19
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
19
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, LIN, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
N
Near Data Space ................................................................ 34
O
On-Chip Voltage Regulator ............................................... 287
Oscillator Configuration..................................................... 107
Output Compare
Output Compare with Dedicated Timers ........................... 161
P
Packaging ......................................................................... 327
Parallel Master Port. See PMP. ........................................ 231
Peripheral Enable Bits ...................................................... 125
Peripheral Module Disable Bits ......................................... 125
Peripheral Pin Select (PPS) .............................................. 129
Pin Diagrams ................................................................ 4, 5, 6
Pinout Descriptions ............................................................. 13
Power-Saving Features .................................................... 117
Product Identification System ........................................... 350
Program Memory
Program Space Visibility (PSV) .......................................... 53
Program Verification ......................................................... 289
Pulse-Width Modulation (PWM) Mode .............................. 164
Pulse-Width Modulation. See PWM.
PWM
R
Reader Response ............................................................. 349
Reference Clock Output.................................................... 115
Register Maps
2010 Microchip Technology Inc.
BOR .......................................................................... 288
POR .......................................................................... 287
Power-up Requirements ........................................... 288
Standby Mode........................................................... 288
Tracking .................................................................... 287
Clock Selection ......................................................... 108
Clock Switching......................................................... 112
Initial Configuration on POR ..................................... 108
Secondary Oscillator (SOSC) ................................... 115
USB Operation.......................................................... 114
32-Bit Mode............................................................... 161
Operations ................................................................ 163
Subcycle Resolution ................................................. 166
Synchronous and Trigger Modes.............................. 161
Details ....................................................................... 329
Marking ..................................................................... 327
Available Peripherals and Pins ................................. 129
Configuration Control ................................................ 132
Considerations for Use ............................................. 133
Input Mapping ........................................................... 130
Output Mapping ........................................................ 131
Peripheral Priority ..................................................... 129
Clock Frequency and Clock Switching...................... 117
Access Using Table Instructions................................. 52
Address Space............................................................ 31
Addressing .................................................................. 50
Flash Configuration Words ......................................... 32
Memory Maps ............................................................. 31
Organization................................................................ 32
Program Space Visibility ............................................. 53
Duty Cycle and Period .............................................. 165
A/D Converter ............................................................. 43
Comparators ............................................................... 46
Sequence.......................................................... 113
Special Considerations ..................................... 114
PIC24FJ64GB004 FAMILY
Registers
CPU Core ................................................................... 35
CRC............................................................................ 46
CTMU ......................................................................... 43
Deep Sleep................................................................. 48
I
ICN ............................................................................. 36
Input Capture.............................................................. 39
Interrupt Controller...................................................... 37
NVM............................................................................ 48
Output Compare ......................................................... 40
Pad Configuration....................................................... 43
Parallel Master/Slave Port .......................................... 45
Peripheral Pin Select .................................................. 47
PMD............................................................................ 49
PORTA ....................................................................... 42
PORTB ....................................................................... 42
PORTC ....................................................................... 42
RTCC.......................................................................... 46
SPI.............................................................................. 42
System........................................................................ 48
Timers......................................................................... 38
UART.......................................................................... 41
USB OTG ................................................................... 44
AD1CHS (A/D Input Select)...................................... 264
AD1CON1 (A/D Control 1)........................................ 261
AD1CON2 (A/D Control 2)........................................ 262
AD1CON3 (A/D Control 3)........................................ 263
AD1CSSL (A/D Input Scan Select)........................... 266
AD1PCFG (A/D Port Configuration) ......................... 265
ALCFGRPT (Alarm Configuration) ........................... 245
ALMINSEC (Alarm Minutes and
ALMTHDY (Alarm Month and Day Value) ................ 248
ALWDHR (Alarm Weekday and Hours Value) ......... 248
BDnSTAT Prototype (Buffer Descriptor n
BDnSTAT Prototype (Buffer Descriptor n
CLKDIV (Clock Divider) ............................................ 111
CMSTAT (Comparator Module Status) .................... 272
CMxCON (Comparator x Control) ............................ 271
CORCON (CPU Control) ............................................ 29
CORCON (CPU Core Control) ................................... 73
CRCCON1 (CRC Control 1) ..................................... 256
CRCCON2 (CRC Control 2) ..................................... 257
CRCXORH (CRC XOR Polynomial, High Byte) ....... 258
CRCXORL (CRC XOR Polynomial, Low Byte)......... 257
CTMUCON (CTMU Control)..................................... 277
CTMUICON (CTMU Current Control) ....................... 278
CVRCON (Comparator Voltage
CW1 (Flash Configuration Word 1) .......................... 280
CW2 (Flash Configuration Word 2) .......................... 282
CW3 (Flash Configuration Word 3) .......................... 284
DEVID (Device ID).................................................... 286
DEVREV (Device Revision)...................................... 286
DSCON (Deep Sleep Control).................................. 123
DSWAKE (Deep Sleep Wake-up Source) ................ 124
I2CxCON (I2Cx Control)........................................... 184
I2CxMSK (I2Cx Slave Mode Address Mask)............ 188
I2CxSTAT (I2Cx Status) ........................................... 186
ICxCON1 (Input Capture x Control 1)....................... 159
ICxCON2 (Input Capture x Control 2)....................... 160
IEC0 (Interrupt Enable Control 0) ............................... 82
2
C .............................................................................. 41
Seconds Value) ................................................ 249
Status, CPU Mode)........................................... 205
Status, USB Mode)........................................... 204
Reference Control) ........................................... 274
DS39940D-page 345