AT89C5122D-PSTUM Atmel, AT89C5122D-PSTUM Datasheet - Page 40

• Manufacturer Part Number: AT89C5122D-PSTUM
• Description: IC 8051 MCU FLASH 32K 64QFN
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-PSTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Phase Lock Loop (PLL)
PLL Description
PLL Programming
40
AT83R5122, AT8xC5122/23
CK_XTAL1
The AT83R5122, AT8xC5122/23’s PLL is used to generate internal high frequency
clock synchronized with an external low-frequency. Figure 16 shows the internal struc-
ture of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Figure 17). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
duced by the charge pump. It generates a square wave signal: the PLL clock. The
CK_PLL frequency is defined by the follwing formula:
F
Figure 16. PLL Block Diagram and Symbol
Figure 17. PLL Filter Value
The PLL must be programmed to work at 96 MHz frequency by means of PLLCON and
PLLDIV registers. As soon as the PLL is enabled, the firmware must wait for the lock bit
status to ensure that the PLL is ready.
PLLF
CK_PLL
= F
150 pF
1,8
N Divider
N3:0
CK_XTAL1
K
VSS
* (R+1) / (N+1)
VSS
33 pF
PLLCON.1
PLLCON.0
PLOCK
PLLEN
PFLD
Down
Up
R divider
R3:0
PLLF
CHP
V
REF
VCO
4202F–SCR–07/2008
CK_PLL
REF
pro-