PIC16F747-I/ML Microchip Technology, PIC16F747-I/ML Datasheet - Page 40

• Manufacturer Part Number: PIC16F747-I/ML
• Description: IC PIC MCU FLASH 4KX14 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F747-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: AUSART, CCP, I2C, MSSP, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 8
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3DBF777 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F7X7
4.6.3
When clock switching is performed, the Watchdog
Timer is disabled because the Watchdog Ripple
Counter is used as the Oscillator Start-up Timer (OST).
REGISTER 4-2:
DS30498C-page 38
Note:
CLOCK TRANSITION AND WDT
The OST is only used when switching to
XT, HS and LP Oscillator modes.
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
IRCF<2:0>: Internal RC Oscillator Frequency Select bits
000 = 31.25 kHz
001 = 125 kHz
010 = 250 kHz
011 = 500 kHz
100 = 1 MHz
101 = 2 MHz
110 = 4 MHz
111 = 8 MHz
OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the primary system clock
0 = Device is running from the Timer1 oscillator (T1OSC) or INTRC as a secondary system clock
IOFS: INTOSC Frequency Stable bit
1 = Frequency is stable
0 = Frequency is not stable
SCS<1:0>: Oscillator Mode Select bits
00 = Oscillator mode defined by FOSC<2:0>
01 = T1OSC is used for system clock
10 = Internal RC is used for system clock
11 = Reserved
bit 7
Legend:
R = Readable bit
-n = Value at POR
OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh)
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the oscillator
U-0
—
mode.
R/W-0
IRCF2
R/W-0
IRCF1
W = Writable bit
‘1’ = Bit is set
IRCF0
R/W-0
Once the clock transition is complete (i.e., new oscilla-
tor selection switch has occurred), the Watchdog
Counter is re-enabled with the Counter Reset. This
allows the user to synchronize the Watchdog Timer to
the start of execution at the new clock frequency.
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OSTS
R-0
(1)
IOFS
R-0
 2004 Microchip Technology Inc.
x = Bit is unknown
R/W-0
SCS1
R/W-0
SCS0
bit 0