AT89C51RE2-SLSUM Atmel, AT89C51RE2-SLSUM Datasheet - Page 50

• Manufacturer Part Number: AT89C51RE2-SLSUM
• Description: MCU 8BIT FLASH 2.7-5.5V 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Package: 44PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Operation Cross Memory Access
Sharing Instructions
50
AT89C51RE2
Space addressable in read and write are:
•
•
•
•
•
•
•
•
The table below provide the different kind of memory which can be accessed from different code
location.
Table 27. Cross Memory Access
Table 28. Instructions shared
Note:
Action
or BANK3
boot RM0
External
Read
Write
memory
EA = 0
RAM
ERAM (Expanded RAM access by movx)
XRAM (eXternal RAM)
FM0 (user flash)
Hardware byte
XROW FM0
Boot RM0
Flash Column latch
FM0
by cl: using Column Latch
RAM
Action
MOV
MOV
Read
Read
Read
Write
Write
Write
RAM
A,@DPTR
@DPTR,A
ok
ok
ok
ok
ok
ok
XRAM
MOVX
MOVX
XRAM
ERAM
ok
ok
ok
ok
ok
ok
@A+DPTR
MOVC A,
RM0
boot RM0
-
ok
-
-
-
-
-
@DPTR,A
CL FM0
MOVX
ok (RWW)
ok (idle)
-
FM0
ok
ok
-
-
@A+DPTR
MOVC A,
FM0
by CL
ok (RWW)
FM0
HSB
ok
ok
ok
-
-
@A+DPTR
MOVC A,
ok (RWW)
HSB
by CL
FM0
FCB
ok
ok
ok
-
-
7663E–8051–10/08
XAF FM0
@A+DPTR
XAF FM0
ok (RWW)
MOVC A,
by CL
FM0
ok
ok
ok
-
-