LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 19

IC MCU 32BIT 32KB FLASH 48LQFP

LPC1313FBD48,151

Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheets

Specifications of LPC1313FBD48,151

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151

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NXP Semiconductors
LPC1311_13_42_43
Product data sheet
7.9.1.1 Features
7.9.1 Full-speed USB device controller
7.10 UART
7.9 USB interface (LPC1342/43 only)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1342/43 USB interface is a device controller with on-chip PHY for device
functions.
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
Table 5.
The LPC1311/13/42/43 contains one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
Logical
endpoint
0
0
1
1
2
2
3
3
4
4
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per
endpoint (see
Supports Control, Bulk, Isochronous, and Interrupt endpoints.
Supports SoftConnect feature.
Double buffer implementation for Bulk and Isochronous endpoints.
USB device endpoint configuration
Physical
endpoint
0
1
2
3
4
5
6
7
8
9
All information provided in this document is subject to legal disclaimers.
Table
Rev. 3 — 10 August 2010
Endpoint type
Control
Control
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Isochronous
Isochronous
5).
Direction
out
in
out
in
out
in
out
in
out
in
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
Packet size
(byte)
64
64
64
64
64
64
64
64
512
512
© NXP B.V. 2010. All rights reserved.
Double buffer
no
no
no
no
no
no
yes
yes
yes
yes
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