LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 46

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
Table 17.
[1]
[2]
[3]
[4]
LPC1311_13_42_43
Product data sheet
Symbol
SSP master
T
t
t
t
t
SSP slave
T
t
t
t
t
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
cy(clk)
cy(PCLK)
T
main clock frequency f
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
= −40 °C to +85 °C.
= 25 °C; V
= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f
= 12 × T
Dynamic characteristics: SSP pins in SPI mode
Parameter
clock cycle time
data set-up time
data hold time
data output valid time
data output hold time
PCLK cycle time
data set-up time
data hold time
data output valid time
data output hold time
10.6 SSP interface
cy(PCLK)
DD
= 3.3 V.
main
.
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
Conditions
when only receiving
when only transmitting
in SPI mode;
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
2.4 V ≤ V
2.0 V ≤ V
All information provided in this document is subject to legal disclaimers.
main
Rev. 3 — 10 August 2010
DD
DD
. The clock cycle time derived from the SPI bit rate T
≤ 3.6 V
< 2.4 V
[1]
[1]
[2]
[2]
[2]
[2]
[2]
[3][4]
[3][4]
[3][4]
[3][4]
Min
40
27.8
15
20
0
-
0
13.9
0
3 × T
-
-
cy(PCLK)
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
+ 4
Max
-
-
-
-
-
10
-
-
-
-
3 × T
2 × T
cy(PCLK)
cy(PCLK)
cy(clk)
© NXP B.V. 2010. All rights reserved.
is a function of the
+ 11
+ 5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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