LPC2460FBD208,551 NXP Semiconductors, LPC2460FBD208,551 Datasheet - Page 36
LPC2460FBD208,551
Manufacturer Part Number
LPC2460FBD208,551
Description
IC ARM7 MCU ROMLESS 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FBD208,551
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4259
935282455551
LPC2460FBD208-S
935282455551
LPC2460FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP
Quantity:
180
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
3.3.1.1 Examples of AHB1 settings
3.3.2 AHB Arbiter Configuration register 2 (AHBCFG2 - 0xE01F C18C)
The following examples use the LPC2478 to illustrate how to select the priority of each
AHB1 master based on different system requirements.
Table 31.
Table 32.
Table 33.
[1]
Table 34.
[1]
By default, the AHB2 access is scheduled round-robin (bit 0 = 1). For round-robin
scheduling, the default priority sequence will be Ethernet and CPU.
The AHB2 access priority can be configured as priority scheduling (bit 0 = 0) and priority
of the each of the AHB2 bus masters can be set by writing the priority value (highest
priority = 2, lowest priority = 1).
Bit
14:12
18:16
22:20
26:24
30:28
Bit
14:12
18:16
22:20
26:24
30:28
Bit
14:12
18:16
22:20
26:24
30:28
Bit
14:12
18:16
22:20
26:24
30:28
Sequence based on round-robin.
Sequence based on round-robin.
Symbol
EP1
EP2
EP3
EP4
EP5
Symbol
EP1
EP2
EP3
EP4
EP5
Symbol
EP1
EP2
EP3
EP4
EP5
Symbol
EP1
EP2
EP3
EP4
EP5
Priority sequence (bit 0 = 0): GPDMA, AHB1, CPU, LCD, USB
Priority sequence (bit 0 = 0): USB, LCD, AHB1, CPU, GPDMA
Priority sequence (bit 0 = 0): LCD, CPU, GPDMA, AHB1, USB
Priority sequence (bit 0 = 0): USB, AHB1, CPU, GPDMA, LCD
Description Priority value nnn
CPU
GPDMA
AHB1
USB
LCD
Description Priority value nnn
CPU
GPDMA
AHB1
USB
LCD
Description Priority value nnn
CPU
GPDMA
AHB1
USB
LCD
Description Priority value nnn
GPDMA
USB
LCD
CPU
AHB1
Rev. 04 — 26 August 2009
100 (4)
011 (3)
010 (2)
001 (1)
101 (5)
011 (3)
010 (2)
100 (4)
101 (5)
001 (1)
011 (3)
100 (4)
100 (4)
001 (1)
010 (2)
000
000
011 (3)
001 (1)
010 (2)
Chapter 3: LPC24XX System control
Priority sequence
2
3
4
5
1
Priority sequence
3
4
2
1
5
Priority sequence
3
1
2
5
4
Priority sequence
4
5
1
3
2
[1]
[1]
[1]
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
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