ADUC841BSZ62-5 Analog Devices Inc, ADUC841BSZ62-5 Datasheet - Page 26

IC ADC/DAC 12BIT W/MCU 52-MQFP

ADUC841BSZ62-5

Manufacturer Part Number
ADUC841BSZ62-5
Description
IC ADC/DAC 12BIT W/MCU 52-MQFP
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC841BSZ62-5

Core Size
8-Bit
Program Memory Size
62KB (62K x 8)
Core Processor
8052
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, PSM, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-MQFP, 52-PQFP
Controller Family/series
(8051) 8052
No. Of I/o's
32
Ram Memory Size
2.25KB
Cpu Speed
20MIPS
No. Of Timers
3
No. Of Pwm Channels
2
Embedded Interface Type
UART
Rohs Compliant
Yes
Cpu Family
ADuC8xx
Device Core
8052
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SPI/UART
Total Internal Ram Size
2.25KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
On-chip Adc
8-chx12-bit
On-chip Dac
2-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Manufacturer
Quantity
Price
Part Number:
ADUC841BSZ62-5
Manufacturer:
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ADUC841BSZ62-5
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Quantity:
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ADuC841/ADuC842/ADuC843
ADCCON3—(ADC Control SFR 3)
The ADCCON3 register controls the operation of various
calibration modes and also indicates the ADC busy status.
SFR Address
SFR Power-On Default
Bit Addressable
Table 9. ADCCON3 SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Name
BUSY
RSVD
AVGS1
AVGS0
RSVD
RSVD
TYPICAL
SCAL
Description
ADC Busy Status Bit.
A read-only status bit that is set during a valid ADC conversion or during a calibration cycle.
Busy is automatically cleared by the core at the end of conversion or calibration.
Reserved. This bit should always be written as 0.
Number of Average Selection Bits.
This bit selects the number of ADC readings that are averaged during a calibration cycle.
AVGS1
0
0
1
1
Reserved. This bit should always be written as 0.
This bit should always be written as 1 by the user when performing calibration.
Calibration Type Select Bit.
This bit selects between offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for offset calibration.
Set to 1 for gain calibration.
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle.
It is automatically cleared when the calibration cycle is completed.
F5H
00H
No
AVGS0
0
1
0
1
Rev. 0 | Page 26 of 88
Number of Averages
15
1
31
63

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