ADUC841BSZ62-5 Analog Devices Inc, ADUC841BSZ62-5 Datasheet - Page 35

• Manufacturer Part Number: ADUC841BSZ62-5
• Description: IC ADC/DAC 12BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC841BSZ62-5

• Core Size: 8-Bit
• Program Memory Size: 62KB (62K x 8)
• Core Processor: 8052
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: DMA, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 2.25KB
• Cpu Speed: 20MIPS
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 8-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Example: Programming the Flash/EE Data Memory
A user wants to program F3H into the second byte on Page 03H
of the Flash/EE data memory space while preserving the other
3 bytes already in this page. A typical program of the Flash/EE
data array involves
1.
2.
3.
Step 1: Set Up the Page Address
Address registers EADRH and EADRL hold the high byte
address and the low byte address of the page to be addressed.
The assembly language to set up the address may appear as
MOV EADRH,#0
MOV EADRL,#03H
Step 2: Set Up the EDATA Registers
Write the four values to be written into the page into the four
SFRs, EDATA1–4. Unfortunately, the user does not know three
of them. Thus, the user must read the current page and over-
write the second byte.
MOV ECON,#1
MOV EDATA2,#0F3H
Step 3: Program Page
A byte in the Flash/EE array can be programmed only if it has
previously been erased. To be more specific, a byte can be
programmed only if it already holds the value FFH. Because of
the Flash/EE architecture, this erase must happen at a page level;
therefore, a minimum of 4 bytes (1 page) are erased when an
erase command is initiated. Once the page is erase, the user can
program the 4 bytes in-page and then perform a verification of
the data.
MOV ECON,#5
MOV ECON,#2
MOV ECON,#4
MOV A,ECON
JNZ ERROR
Although the 4 kBytes of Flash/EE data memory are shipped
from the factory pre-erased, i.e., byte locations set to FFH, it is
nonetheless good programming practice to include an
ERASEALL routine as part of any configuration/setup code
running on the parts. An ERASEALL command consists of
writing 06H to the ECON SFR, which initiates an erase of the
4-kByte Flash/EE array. This command coded in 8051 assembly
would appear as
MOV ECON,#06H
Setting EADRH/L with the page address.
Writing the data to be programmed to the EDATA1–4.
Writing the ECON SFR with the appropriate command.
; Set Page Address Pointer
; Read Page into EDATA1-4
; Overwrite byte 2
; ERASE Page
; WRITE Page
; VERIFY Page
; Check if ECON=0 (OK!)
; Erase all Command
; 2 ms Duration
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Flash/EE Memory Timing
Typical program and erase times for the parts are as follows:
Normal Mode (operating on Flash/EE data memory)
READPAGE (4 bytes)
WRITEPAGE (4 bytes)
VERIFYPAGE (4 bytes)
ERASEPAGE (4 bytes)
ERASEALL (4 kBytes)
READBYTE (1 byte)
WRITEBYTE (1 byte)
ULOAD Mode (operating on Flash/EE program memory)
WRITEPAGE (256 bytes)
ERASEPAGE (64 bytes)
ERASEALL (56 kBytes)
WRITEBYTE (1 byte)
Note that a given mode of operation is initiated as soon as the
command word is written to the ECON SFR. The core micro-
controller operation on the parts is idled until the requested
program/read or erase mode is completed. In practice, this
means that even though the Flash/EE memory mode of operation
is typically initiated with a two machine cycle MOV instruction
(to write to the ECON SFR), the next instruction is not executed
until the Flash/EE operation is complete. This means that the
core cannot respond to interrupt requests until the Flash/EE
operation is complete, although the core peripheral functions
like counter/timers continue to count and time as configured
throughout this period.
ADuC841/ADuC842/ADuC843
22 machine cycles
380 µs
22 machine cycles
2 ms
2 ms
9 machine cycles
200 µs
16.5 ms
2 ms
2 ms
200 µs