LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 78

• Manufacturer Part Number: LPC2478FBD208,551
• Description: IC ARM7 MCU 512K LCD 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2478FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
• Development Tools By Supplier: OM11015, OM11019, OM11022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4363; 935284069551; LPC2478FBD208-S

NXP Semiconductors
UM10237_4
User manual
10.2 EMC Status register (EMCStatus - 0xFFE0 8004)
Table 68.
[1]
The read-only EMCStatus register provides EMC status information.
the bit assignments for the EMCStatus register.
Table 69.
Bit
2
31:3
Bit
0
1
2
31:3 -
The external memory cannot be accessed in low-power or disabled state. If a memory access is performed
an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled
state.
Symbol
Busy (B)
Write buffer
status (S)
Self-refresh
acknowledge
(SA)
Symbol
Low-power mode
(L)
-
EMC Control register (EMCControl - address 0xFFE0 8000) bit description
EMC Status register (EMCStatus - address 0xFFE0 8008) bit description
Rev. 04 — 26 August 2009
Value
0
1
0
1
0
1
-
Value Description
0
1
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Indicates normal, or low-power mode:
Normal mode (warm reset value).
Low-power mode.
Entering low-power mode reduces memory controller
power consumption. Dynamic memory is refreshed as
necessary. The memory controller returns to normal
functional mode by clearing the low-power mode bit
(L), or by POR.
This bit must only be modified when the EMC is in idle
state.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
Description
This bit is used to ensure that the memory controller
enters the low-power or disabled mode cleanly by
determining if the memory controller is busy or not:
EMC is idle (warm reset value).
EMC is busy performing memory transactions,
commands, auto-refresh cycles, or is in self-refresh
mode (POR reset value).
This bit enables the EMC to enter low-power mode
or disabled mode cleanly:
Write buffers empty (POR reset value)
Write buffers contain data.
This bit indicates the operating mode of the EMC:
Normal mode
Self-refresh mode (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
[1]
Table 5–69
UM10237
© NXP B.V. 2009. All rights reserved.
shows
78 of 792
Reset
Value
1
0
1
NA
Reset
Value
0
NA