STM8S105C4T6 STMicroelectronics, STM8S105C4T6 Datasheet - Page 19

• Manufacturer Part Number: STM8S105C4T6
• Description: MCU 16KB FLASH MEM 16MHZ 48LQFP
• Manufacturer: STMicroelectronics
• Series: STM8Sr

Specifications of STM8S105C4T6

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.95 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: STM8S10x
• Core: STM8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWSTM8
• Development Tools By Supplier: STICE-SYS001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8818

STM8S105xx
4.14.2
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Asynchronous communication (UART mode)
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Synchronous communication
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LIN master mode
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LIN slave mode
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SPI
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LIN master mode
LIN slave mode
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
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Transmission error detection with interrupt generation
Parity control
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
Emission: Generates 13-bit synch break frame
Reception: Detects 11-bit break frame
Autonomous header handling - one single interrupt per valid message header
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
Synch delimiter checking
11-bit LIN synch break detection - break detection always active
Parity check on the LIN identifier field
LIN error management
Hot plugging support
Maximum speed: 8 Mbit/s (f
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
Address bit (MSB)
Idle line (interrupt)
DocID14771 Rev 10
MASTER
/2) both for master and slave
CPU
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CPU
/16) and capable of
Product overview
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