STM32F100RBH6B STMicroelectronics, STM32F100RBH6B Datasheet - Page 61
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STM32F100RBH6B
Manufacturer Part Number
STM32F100RBH6B
Description
MCU 32BIT ARM 128K FLASH 64LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F100R4T6B.pdf
(87 pages)
Specifications of STM32F100RBH6B
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
STM32F100x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
51
Number Of Timers
6
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STM32100B-EVAL
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
STM32100B-EVAL - EVAL BOARD FOR STM32F100VBT6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-10495
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F100RBH6B
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
STM32F100RBH6BTR
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
5.3.14
Figure 26. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
Table 37.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 27. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
Table
NF(NRST)
IH(NRST)
IL(NRST)
Symbol
F(NRST)
the series resistance must be minimum
Table
hys(NRST)
R
PU
37. Otherwise the reset will not be taken into account by the device.
8.
(1)
(1)
(1)
(1)
PU
NRST pin characteristics
(see
EXT ERNAL
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) ≤ 2/3)T and if the duty cycle is (45-55%)
Table
34).
Parameter
t r(I O)out
Doc ID 16455 Rev 6
(~10% order)
10%
50%
when loaded by 50pF
90%
.
(2)
Conditions
V
DD
IN
T
10%
=
supply voltage conditions summarized
Table 37
V
SS
50%
90%
t r(I O)out
–0.5
Min
300
30
2
are derived from tests
IL(NRST)
Electrical characteristics
max level specified in
Typ
200
40
V
DD
Max
100
0.8
50
+0.5
ai14131
Unit
to
61/87
mV
kΩ
ns
ns
V