HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 151

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.40 (2) NEG (W)
Notes
An overflow occurs if the previous contents of Rd was H'8000.
NEG (NEGate)
Operation
0 – Rd
Assembly-Language Format
NEG.W Rd
Operand Size
Word
Description
This instruction takes the two’s complement of the contents of a 16-bit register Rd (destination
operand) and stores the result in the 16-bit register Rd (subtracting the register contents from
H'0000). If the original contents of Rd was H'8000, however, the result remains H'8000.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Register direct
Addressing
Mode
Rd
Mnemonic
NEG.W
Operands
Rd
1st byte
1
7
Condition Code
H: Set to 1 if there is a borrow at bit 11;
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Set to 1 if there is a borrow at bit 15;
2nd byte
9
otherwise cleared to 0.
cleared to 0.
cleared to 0.
cleared to 0.
otherwise cleared to 0.
Instruction Format
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Rev. 3.00 Dec 13, 2004 page 135 of 258
I
rd
UI
Section 2 Instruction Descriptions
H
3rd byte
—
U
Negate Binary Signed
N
4th byte
REJ09B0213-0300
Z
V
States
No. of
C
2