HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 180
![IC H8 MCU FLASH 56K 64LQFP](/photos/12/19/121969/hd64f3687gfpv_sml.jpg)
HD64F3687GFPV
Manufacturer Part Number
HD64F3687GFPV
Description
IC H8 MCU FLASH 56K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of HD64F3687GFPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Package
64LQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
45
Interface Type
I2C/SCI
On-chip Adc
8-chx10-bit
Number Of Timers
3
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3687GFPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (2Mb)
Section 2 Instruction Descriptions
2.2.53 (1) SHAL (B)
SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift)
Assembly-Language Format
SHAL.B Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The
most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Rev. 3.00 Dec 13, 2004 page 164 of 258
REJ09B0213-0300
Register direct
Addressing
Mode
Mnemonic
SHAL.B
C
Rd
MSB
Operands
b
7
Rd
1st byte
. . . . . .
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 7.
2nd byte
8
cleared to 0.
cleared to 0.
cleared to 0.
Instruction Format
— —
I
rd
UI
— —
H
3rd byte
LSB
b
0
U
N
0
4th byte
Shift Arithmetic
Z
V
States
No. of
C
2
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