HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 92
![IC H8 MCU FLASH 56K 64LQFP](/photos/12/19/121969/hd64f3687gfpv_sml.jpg)
HD64F3687GFPV
Manufacturer Part Number
HD64F3687GFPV
Description
IC H8 MCU FLASH 56K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of HD64F3687GFPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Package
64LQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
45
Interface Type
I2C/SCI
On-chip Adc
8-chx10-bit
Number Of Timers
3
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3687GFPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 2 Instruction Descriptions
2.2.23 DAA
DAA (Decimal Adjust Add)
Operation
Rd (decimal adjust)
Assembly-Language Format
DAA Rd
Operand Size
Byte
Description
Given that the result of an addition operation performed by an ADD.B or ADDX instruction on
4-bit BCD data is contained in an 8-bit register Rd (destination register) and the carry and half-
carry flags, the DAA instruction adjusts the general register contents by adding H'00, H'06, H'60,
or H'66 according to the table below.
Available Registers
Rd: R0L to R7L, R0H to R7H
Rev. 3.00 Dec 13, 2004 page 76 of 258
REJ09B0213-0300
Adjustment
C Flag
before
0
0
0
0
0
0
1
1
1
Upper 4 Bits
Adjustment
before
A to F
A to F
0 to 9
0 to 8
0 to 9
9 to F
1 to 2
1 to 2
1 to 3
Rd
Adjustment
H Flag
before
0
0
1
0
0
1
0
0
1
Lower 4 Bits
Adjustment
Condition Code
H: Undetermined (no guaranteed value).
N: Set to 1 if the adjusted result is negative;
Z: Set to 1 if the adjusted result is zero;
V: Undetermined (no guaranteed value).
C: Set to 1 if there is a carry at bit 7;
before
A to F
A to F
A to F
0 to 9
0 to 3
0 to 9
0 to 3
0 to 9
0 to 3
otherwise cleared to 0.
otherwise cleared to 0.
otherwise left unchanged.
— —
I
UI
(hexadecimal)
H
*
Value Added
—
U
00
06
06
60
66
66
60
66
66
N
Decimal Adjust
Z
Adjustment
V
*
C Flag
after
0
0
0
1
1
1
1
1
1
C
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