MC56F8367VPYE Freescale Semiconductor, MC56F8367VPYE Datasheet
MC56F8367VPYE
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MC56F8367VPYE Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8367 Rev. 8 01/2007 freescale.com ...
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... Technical Data, Rev. 8 Table 10-1.; also removed Table 10-4 and additional minor for MOSI0 and MISO0 Table 2-2. Clarified external reference and Table 11-2; replaced “Tri-stated” Table 2-2. Table 2-2: Table 2- the design used through a 1K resistor. SS Freescale Semiconductor Preliminary ...
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... GPIOE 2 FlexCAN SPI0 or SCI1 or GPIOE GPIOD 4 Freescale Semiconductor Preliminary • Temperature Sensor • two Quadrature Decoders • Optional on-chip regulator • two FlexCAN modules • Two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interfaces (SPIs) • four general-purpose Quad Timers • ...
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... Thermal Design Considerations . . . . . . . 177 12.2. Electrical Design Considerations . . . . . . 178 12.3. Power Distribution and I/O Ring Part 13: Ordering Information . . . . . . . . . . 180 56F8367 Technical Data, Rev. 8 Interrupt Timing . . . . . . . . . . . . . 151 (SPI) Timing . . . . . . . . . . . . . . . . . 153 (SCI) Timing . . . . . . . . . . . . . . . . 158 (ADC) Parameters . . . . . . . . . . . 161 Information . . . . . . . . . . . . . . . . . . 166 Information . . . . . . . . . . . . . . . . . 173 Implementation . . . . . . . . . . . . . . 179 Freescale Semiconductor Preliminary ...
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... Table 1-1 outlines the key differences between the 56F8367 and 56F8167 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quad Timer Quadrature Decoder Temperature Sensor Dedicated GPIO Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8367 60MHz/60 MIPS 4KB 32KB — ...
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... In the 56F8167, two general-purpose Quad Timers; Timer A works in conjunction with Quadrature Decoder 0 or GPIO and Timer C works in conjunction with GPIO • two FlexCAN (CAN Version 2.0 B-compliant) modules with 2-pin port for transmit and receive 6 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... The 56F8367 and 56F8167 support program execution from internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Device Description ...
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... Program Flash memory area, which can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes and the Boot Flash memory can also be either bulk or page erased. 8 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Award-Winning Development Environment ...
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... The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. 10 Figure 1-1 and Figure 56F8367 Technical Data, Rev. 8 1-2. Figure 1-1 illustrates how the Part 2, Signal/Connection Freescale Semiconductor Preliminary ...
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... I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. Freescale Semiconductor Preliminary pab[20:0] cdbw[31:0] xab1[23:0] ...
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... V V REFN Figure 1-2 Peripheral Subsystem 56F8367 Technical Data, Rev. 8 Interrupt Low Voltage Interrupt System POR RESET SIM COP Reset COP 2 FlexCAN 2 FlexCAN2 13 PWMA SYNC Output 13 ch2i 2 Timer C ch2o 8 8 ADCA REFH REFP REFMID , and V pins. REFLO Freescale Semiconductor , Preliminary ...
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... Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. Freescale Semiconductor Preliminary Table 1-2 Bus Signal Names Function ...
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... Freescale Literature Distribution Table 1-3 Chip Documentation Description Logic State True False True False 56F8367 Technical Data, Rev. 8 Centers, or online Order Number DSP56800EERM MC56F8300UM MC56F83xxBLUM MC56F8367 MC56F8367E MC56F8167E Signal State 1 Voltage Asserted Deasserted Asserted Deasserted Freescale Semiconductor Preliminary at ...
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... Temperature Sense Dedicated GPIO 1. If the on-chip regulator is disabled, the V 2. Alternately, can function as Quad Timer pins 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO Freescale Semiconductor Preliminary Figure 2-1. In Table 2-2, each table row describes the signal or signals 2 pins serve as 2 ...
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... Technical Data, Rev. 8 Quadrature Decoder 0 or Quad Timer A SPI0 or GPIO Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO PWMA PWMB ADCA REF ADCB Temperature Sense FlexCAN Quad Timer C and D or GPIO INTERRUPT/ PROGRAM CONTROL . 1 (160-pin LQFP) Freescale Semiconductor Preliminary ...
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... TXD1 (GPIOD6) SCI 1 RXD1 (GPIOD7) or GPIO JTAG/ EOnCE Port * When the on-chip regulator is disabled, these four pins become 2.5V V Figure 2-2 56F8167 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. Freescale Semiconductor Preliminary V DD_IO DDA_ADC 1 1 ...
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... It must be connected to a clean analog power supply. Oscillator and PLL Power — This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. 56F8367 Technical Data, Rev. 8 Signal Description Freescale Semiconductor Preliminary ...
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... CLKMODE 99 H12 EXTAL 94 J12 Freescale Semiconductor Preliminary State Type During Reset V — These pins provide ground for chip logic and I/O drivers. SS ADC Analog Ground — This pin supplies an analog ground to the ADC modules. Input Input On-Chip Regulator Disable — ...
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... After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA8, clear bit 8 in the GPIOA_PUR register. 56F8367 Technical Data, Rev. 8 Signal Description for details. Freescale Semiconductor Preliminary ...
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... A13 24 J1 (GPIOA5) A14 25 J2 (GPIOA6) A15 26 J3 (GPIOA7) Freescale Semiconductor Preliminary State Type During Reset In reset, Address Bus — specify two of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control ...
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... In these cases, the GPIO_B_PER can be used to individually disable the GPIO. The CLKOSR register in the SIM (see be used to choose between address and clock functions. 56F8367 Technical Data, Rev. 8 Signal Description Table 4-4 for further Part 6.5.7) can then Freescale Semiconductor Preliminary ...
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... D4 88 L14 (GPIOF13 L12 (GPIOF14 L11 (GPIOF15) Freescale Semiconductor Preliminary State Type During Reset Input/ In reset, Data Bus — specify part of the data for external program or output is data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control enabled register (BCR), D0– ...
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... RD is tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register. 56F8367 Technical Data, Rev. 8 Signal Description Freescale Semiconductor Preliminary ...
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... Output (CS0) (GPIOD8) Output Output (CS1) (GPIOD9) Output Freescale Semiconductor Preliminary State Type During Reset In reset, Write Enable — asserted during external memory write output is cycles. When WR is asserted low, pins D0 - D15 become outputs disabled, and the device puts data on the bus. When WR is deasserted pull-up is high, the external data is latched inside the external device ...
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... At reset, this pin is configured as GPIO. This configuration can be changed by setting bit 1 in the GPIO_D_PER register. Then change bit 5 in the SIM_GPS register to select the desired peripheral function. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOD_PUR register. 56F8367 Technical Data, Rev. 8 Signal Description Freescale Semiconductor Preliminary ...
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... TXD0 4 B1 Output (GPIOE0) Output RXD0 5 D2 (GPIOE1) Output Freescale Semiconductor Preliminary State Type During Reset Input/ Input, Port D GPIO — These four GPIO pins can be individually pull-up programmed as input or output pins. enabled Chip Select — CS4 - CS7 may be programmed within the EMI module to act as chip selects for specific areas of the external memory map ...
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... Test Data Output — This tri-stateable output pin provides a serial output is output data stream from the JTAG/EOnCE port driven in the disabled, shift-IR and shift-DR controller states, and changes on the falling pull-up is edge of TCK. enabled 56F8367 Technical Data, Rev. 8 Signal Description through a 2.2K resistor. DD Freescale Semiconductor Preliminary ...
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... Schmitt Output PHASEB0 156 B4 Schmitt (TA1) Schmitt Output (GPIOC5) Schmitt Output Freescale Semiconductor Preliminary State Type During Reset Input, Test Reset — input, a low signal on this pin provides a Input pulled high reset signal to the JTAG TAP controller. To ensure complete internally hardware reset, TRST should be asserted whenever RESET is asserted ...
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... Port E GPIO — This GPIO pin can be individually programmed as Input/ an input or output pin. After reset, the default state is SCLK0. To deactivate the internal pull-up resistor, clear bit 4 in the GPIOE_PUR register. 56F8367 Technical Data, Rev. 8 Signal Description Freescale Semiconductor Preliminary ...
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... Output MISO0 147 D4 Output (GPIOE6) Output SS0 145 D5 (GPIOE7) Output Freescale Semiconductor Preliminary State Type During Reset Input/ In reset, SPI 0 Master Out/Slave In — This serial data pin is an output output is from a master device and an input to a slave device. The master disabled, ...
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... In the 56F8367, the default state after reset is PHASEB1. In the 56F8167, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOC_PUR register. 56F8367 Technical Data, Rev. 8 Signal Description 6.5.8. Freescale Semiconductor Part Preliminary ...
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... Output HOME1 9 E1 Schmitt (TB3) Schmitt Output (SS1) Schmitt (GPIOC3) Schmitt Output Freescale Semiconductor Preliminary State Type During Reset Input, Index1 — Quadrature Decoder 1, INDEX input Input pull-up enabled TB2 — Timer B, Channel 2 Input/ SPI 1 Master In/Slave Out — This serial data pin is an input to a Input/ master device and an output from a slave device ...
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... To deactivate the internal pull-up resistor, set the PWMA1 bit in the SIM_PUDR register. See In reset, PWMB0 - 5 — Six PWMB output pins. output is disabled, pull-up is enabled 56F8367 Technical Data, Rev. 8 Signal Description Part 6.5.8. Part 6.5.8. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...
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... Output V 111 E14 REFMID V 110 F14 REFN V 109 E12 REFLO Freescale Semiconductor Preliminary State Type During Reset Input, ISB0 - 2 — These three input current status pins are used for Input pull-up top/bottom pulse width correction in complementary channel enabled operation for PWMB. ...
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... Port E GPIO — These GPIO pins can be individually Input/ programmed as input or output pins. At reset, these pins default to Timer functionality. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOE_PUR register. 56F8367 Technical Data, Rev. 8 Signal Description Freescale Semiconductor Preliminary ...
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... K9 Schmitt IRQB 66 P9 RESET 98 J14 Schmitt RSTO 97 J13 Output Freescale Semiconductor Preliminary State Type During Reset Input, TD0 - 3— Timer D, Channels and 3 Input/ pull-up enabled Port E GPIO — These GPIO pins can be individually Input/ programmed as input or output pins. At reset, these pins default to Timer functionality. ...
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... Note: When this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the EMI_MODE bit of the SIM_PUDR; see 56F8367 Technical Data, Rev. 8 Signal Description to force the device to DD Table 4-4. Part 6.5.6. in order to DD Table 4-4. Part 6.5.6. Freescale Semiconductor Preliminary ...
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... The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in is shown in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable Freescale Semiconductor Preliminary Prescaler CLK PLLDB PLL F F ÷ ...
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... Z z Note: If the operating temperature range is limited to o below 85 CL2 3 Terminal Sample External Ceramic Resonator Parameters: EXTAL XTAL R = 750 KΩ 56F8367 Technical Data, Rev Meg Ω C (105 C junction), then R z Figure CLKMODE = 0 Figure 3-4. The external clock Freescale Semiconductor 3-3. Preliminary ...
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... Data Flash 32KB Program RAM 4KB Data RAM 32KB Program Boot Flash 32KB Freescale Semiconductor Preliminary Note: When using an external clocking source with EXTAL this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL register V SS should be set to 1. ...
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... Mode 0 – Internal Boot; EMI is configured to use 16 address lines Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin Chip Operating Mode 56F8367 Technical Data, Rev. 8 4-2. Table 4-4 shows the memory Table 4-4. Additional pins must Freescale Semiconductor Preliminary ...
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... The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. Freescale Semiconductor Preliminary 2 EMI_MODE = 0 ...
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... SW Interrupt 1 P:$20 SW Interrupt 0 P:$22 IRQA P:$24 IRQB Reserved P:$28 Low-Voltage Detector (power sense) P:$2A PLL P:$2C FM Access Error Interrupt P:$2E FM Command Complete P:$30 FM Command, data and address Buffers Empty Reserved 56F8367 Technical Data, Rev Interrupt Function 2 2 Freescale Semiconductor Preliminary Part ...
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... TMRD 54 0-2 TMRD 55 0-2 TMRC 56 0-2 TMRC 57 0-2 TMRC 58 0-2 TMRC 59 0-2 Freescale Semiconductor Preliminary Vector Base Address + P:$34 FLEXCAN Bus Off P:$36 FLEXCAN Error P:$38 FLEXCAN Wake Up P:$3A FLEXCAN Message Buffer Interrupt P:$3C GPIO F P:$3E GPIO E P:$40 GPIO D P:$42 ...
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... ADC A Zero Crossing or Limit Error P:$9A Reload PWM B P:$9C Reload PWM A P:$9E PWM B Fault P:$A0 PWM A Fault P:$A2 SW Interrupt LP P:$A4 FlexCAN Bus Off P:$A6 FlexCAN Error P:$A8 FlexCAN Wake Up P:$AA FlexCAN Message Buffer Interrupt 56F8367 Technical Data, Rev (Continued) Interrupt Function Freescale Semiconductor Preliminary ...
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... Flash Memory content, their state is maintained during power down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located between $03_FFF7 and $03_FFFF. Freescale Semiconductor Preliminary Table 4-6 Data Memory Map 2 ...
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... Banked Registers Unbanked Registers FM_BASE + $00 DATA_FLASH_START + $3FFF 32KB DATA_FLASH_START + $0000 Note: Data Flash is NOT available in the 56F8167 device. Sector Size Page Size 16K x 16 bits 1024 x 16 bits 1024 x 16 bits 256 x 16 bits bits 512 x 16 bits Freescale Semiconductor Preliminary ...
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... On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Freescale Semiconductor Preliminary Table 4-8 EOnCE Memory Map ...
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... GPIOF X:$00 F340 SIM X:$00 F350 56F8367 Technical Data, Rev. 8 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 Freescale Semiconductor Preliminary ...
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... CSOR 3 $B CSOR 4 $C CSOR 5 $D CSOR 6 $E CSOR 7 $F CSTC 0 $10 CSTC 1 $11 Freescale Semiconductor Preliminary Prefix Base Address LVI X:$00 F360 FM X:$00 F400 FC X:$00 F800 FC2 X:$00 FA00 (EMI_BASE = $00 F020) Register Description Chip Select Base Address Register 0 Chip Select Base Address Register 1 ...
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... Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A Comparator Status and Control Register 56F8367 Technical Data, Rev. 8 Reset Value 0x016B sets the default number of wait states to 11 for both read and write accesses Freescale Semiconductor Preliminary ...
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... TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSCR Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the 56F8167 device Register Acronym TMRB0_CMP1 TMRB0_CMP2 TMRB0_CAP TMRB0_LOAD TMRB0_HOLD Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description Reserved $20 Compare Register 1 $21 Compare Register 2 $22 ...
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... Load Register $24 Hold Register $25 Counter Register $26 Control Register $27 Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 Freescale Semiconductor Preliminary (TMRB_BASE = $00 F080) Address Offset Register Description $33 Load Register $34 Hold Register $35 Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 ...
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... Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register (TMRD_BASE = $00 F100) Address Offset $0 Compare Register 1 $1 Compare Register 2 $2 Capture Register 56F8367 Technical Data, Rev. 8 Register Description Register Description Freescale Semiconductor Preliminary ...
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... TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR TMRD2_CMPLD1 TMRD2_CMPLD2 TMRD2_COMSCR Freescale Semiconductor Preliminary (TMRD_BASE = $00 F100) Address Offset $3 Load Register $4 Hold Register $5 Counter Register $6 Control Register $7 Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 ...
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... Value Register 1 $8 Value Register 2 $9 Value Register 3 $A Value Register 4 $B Value Register 5 $C Dead Time Register $D Disable Mapping Register 1 $E Disable Mapping Register 2 $F Configure Register $10 Channel Control Register 56F8367 Technical Data, Rev. 8 Register Description Register Description Freescale Semiconductor Preliminary ...
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... PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH Freescale Semiconductor Preliminary (PWMA_BASE = $00 F140) Address Offset Register Description $11 Port Register PWM Internal Correction Control Register $12 (PWMB_BASE = $00 F160) Address Offset Register Description ...
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... Position Difference Counter Hold Register $5 Revolution Counter Register $6 Revolution Hold Register $7 Upper Position Counter Register $8 Lower Position Counter Register $9 Upper Position Hold Register $A Lower Position Hold Register $B Upper Initialization Register $C Lower Initialization Register $D Input Monitor Register 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 ICTL IPR10 Freescale Semiconductor Preliminary (ITCN_BASE = $00 F1A0) Address Offset Register Description $0 Interrupt Priority Register 0 $1 Interrupt Priority Register 1 $2 Interrupt Priority Register 2 $3 Interrupt Priority Register 3 $4 Interrupt Priority Register 4 ...
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... Low Limit Register 7 $19 High Limit Register 0 $1A High Limit Register 1 $1B High Limit Register 2 $1C High Limit Register 3 $1D High Limit Register 4 $1E High Limit Register 5 $1F High Limit Register 6 $20 High Limit Register 7 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... ADCB_ZCC ADCB_LST 1 ADCB_LST 2 ADCB_SDIS ADCB_STAT ADCB_LSTAT ADCB_ZCSTAT ADCB_RSLT 0 ADCB_RSLT 1 ADCB_RSLT 2 ADCB_RSLT 3 ADCB_RSLT 4 ADCB_RSLT 5 ADCB_RSLT 6 ADCB_RSLT 7 ADCB_LLMT 0 Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $21 Offset Register 0 $22 Offset Register 1 $23 Offset Register 2 $24 Offset Register 3 $25 Offset Register 4 $26 Offset Register 5 ...
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... Offset Register 1 $23 Offset Register 2 $24 Offset Register 3 $25 Offset Register 4 $26 Offset Register 5 $27 Offset Register 6 $28 Offset Register 7 $29 Power Control Register ADC Calibration Register $2A (TSENSOR_BASE = $00 F270) Address Offset Register Description $0 Control Register 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Freescale Semiconductor Preliminary (SCI0_BASE = $00 F280) Address Offset Register Description $0 Baud Rate Register $1 Control Register Reserved $3 Status Register ...
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... Interrupt Pending Register $8 Interrupt Edge-Sensitive Register $9 Push-Pull Mode Register $A Raw Data Input Register 56F8367 Technical Data, Rev. 8 Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF — Freescale Semiconductor Preliminary ...
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... GPIOB_RAWDATA Table 4-31 GPIOC Registers Address Map Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Freescale Semiconductor Preliminary (GPIOB_BASE = $00 F300) Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register ...
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... Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF — Freescale Semiconductor Preliminary ...
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... Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL SIM_PCE2 Freescale Semiconductor Preliminary (GPIOF_BASE = $00 F340) Address Offset Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 Interrupt Enable Register ...
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... Information Option Register 1 $1B Not used 16-Bit Information Option Register 2 $1C Room temperature ADC reading of Temperature Sensor; value set during factory test (FC_BASE = $00 F800) Address Offset $0 Module Configuration Register Reserved 56F8367 Technical Data, Rev. 8 Register Description Register Description Freescale Semiconductor Preliminary ...
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... FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $3 Control Register 0 Register $4 Control Register 1 Register $5 Free-Running Timer Register $6 Maximum Message Buffer Configuration Register Reserved $8 Receive Global Mask High Register ...
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... Message Buffer 4 Data Register $65 Message Buffer 4 Data Register $66 Message Buffer 4 Data Register Reserved $68 Message Buffer 5 Control / Status Register $69 Message Buffer 5 ID High Register $6A Message Buffer 5 ID Low Register $6B Message Buffer 5 Data Register $6C Message Buffer 5 Data Register 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $6D Message Buffer 5 Data Register $6E Message Buffer 5 Data Register Reserved $70 Message Buffer 6 Control / Status Register $71 Message Buffer 6 ID High Register ...
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... Message Buffer 12 Data Register Reserved $A8 Message Buffer 13 Control / Status Register $A9 Message Buffer 13 ID High Register $AA Message Buffer 13 ID Low Register $AB Message Buffer 13 Data Register $AC Message Buffer 13 Data Register $AD Message Buffer 13 Data Register $AE Message Buffer 13 Data Register 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... FlexCAN2 is NOT available in the 56F8167 device Register Acronym FC2MCR FC2CTL0 FC2CTL1 FC2TMR FC2MAXMB FC2IMASK2 FC2RXGMASK_H FC2RXGMASK_L FC2RX14MASK_H FC2RX14MASK_L Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description Reserved $B0 Message Buffer 14 Control / Status Register $B1 Message Buffer 14 ID High Register $B2 Message Buffer 14 ID Low Register ...
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... Message Buffer 1 Data Register Reserved $50 Message Buffer 2 Control / Status Register $51 Message Buffer 2 ID High Register $52 Message Buffer 2 ID Low Register $53 Message Buffer 2 Data Register $54 Message Buffer 2 Data Register $55 Message Buffer 2 Data Register $56 Message Buffer 2 Data Register Reserved 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... FC2MB5_DATA FC2MB5_DATA FC2MB5_DATA FC2MB5_DATA FC2MB6_CONTROL FC2MB6_ID_HIGH FC2MB6_ID_LOW FC2MB6_DATA FC2MB6_DATA FC2MB6_DATA FC2MB6_DATA FC2MB7_CONTROL FC2MB7_ID_HIGH Freescale Semiconductor Preliminary (FC2_BASE = $00 FA00) Address Offset Register Description $58 Message Buffer 3 Control / Status Register $59 Message Buffer 3 ID High Register $5A Message Buffer 3 ID Low Register $5B Message Buffer 3 Data Register ...
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... Message Buffer 10 Data Register $94 Message Buffer 10 Data Register $95 Message Buffer 10 Data Register $96 Message Buffer 10 Data Register Reserved $98 Message Buffer 11 Control / Status Register $99 Message Buffer 11 ID High Register $9A Message Buffer 11 ID Low Register $9B Message Buffer 11 Data Register 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... FC2MB13_DATA FC2MB14_CONTROL FC2MB14_ID_HIGH FC2MB14_ID_LOW FC2MB14_DATA FC2MB14_DATA FC2MB14_DATA FC2MB14_DATA FC2MB15_CONTROL FC2MB15_ID_HIGH FC2MB15_ID_LOW FC2MB15_DATA FC2MB15_DATA FC2MB15_DATA Freescale Semiconductor Preliminary (FC2_BASE = $00 FA00) Address Offset Register Description $9C Message Buffer 11 Data Register $9D Message Buffer 11 Data Register $9E Message Buffer 11 Data Register Reserved $A0 Message Buffer 12 Control / Status Register ...
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... Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the Boot Flash memory. 80 (FC2_BASE = $00 FA00) Address Offset Register Description $BE Message Buffer 15 Data Register Reserved 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 SR[9] SR[ Core status register bits indicating current interrupt mask within the core. Freescale Semiconductor Preliminary 4-5, Interrupt Vector Table Contents. 1 Permitted Exceptions 0 Priorities Priorities ...
Page 82
... The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. 82 Current Interrupt Priority 1 Level No Interrupt or SWILP Priorities Priority 0 Priorities Priority 1 Priorities 2, 3 Priorities Priority 3 Part 5.6.30.2 56F8367 Technical Data, Rev. 8 Required Nested Exception Priority Freescale Semiconductor Preliminary ...
Page 83
... A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. Freescale Semiconductor Preliminary any0 Level 0 82-> ...
Page 84
... Interrupt Control Register Reserved Interrupt Priority Register 10 56F8367 Technical Data, Rev. 8 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23 5.6.30 5.6.32 Freescale Semiconductor Preliminary ...
Page 85
... IRQP2 W R $14 IRQP3 W R $15 IRQP4 $16 IRQP5 W Reserved R INT IPIC $1D ICTL W Reserved $1F IPR10 W = Reserved Figure 5-2 ITCN Register Map Summary Freescale Semiconductor Preliminary STPCNT IPL FMERR IPL LOCK IPL GPIOE GPIOF FCMSGBUF IPL FCWKUP IPL IPL IPL SPI1_RCV IPL 0 SCI1_RCV SCI1_RERR IPL ...
Page 86
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1 STPCNT IPL 56F8367 Technical Data, Rev RX_REG IPL TX_REG IPL TRBUF IPL Freescale Semiconductor Preliminary ...
Page 87
... IRQ is priority level 2 • IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 Interrupt Priority Register 2 (IPR2) Freescale Semiconductor Preliminary FMERR IPL LOCK IPL LVI IPL 56F8367 Technical Data, Rev. 8 Register Descriptions ...
Page 88
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 88 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 89
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary FCMSGBUF IPL FCWKUP IPL ...
Page 90
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 90 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 91
... Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary SPI1_RCV ...
Page 92
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 92 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 93
... SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary SCI1_RCV SCI1_RERR ...
Page 94
... IRQ is priority level 1 • IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $ Read TMRC0 IPL TMRD3 IPL Write RESET Figure 5-9 Interrupt Priority Register 6 (IPR6 TMRD2 IPL TMRD1 IPL TMRD0 IPL 56F8367 Technical Data, Rev DEC0_XIRQ DEC0_HIRQ IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 95
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Register Descriptions 95 ...
Page 96
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level TMRB2 IPL TMRB1 IPL TMRB0 IPL 56F8367 Technical Data, Rev TMRC3 IPL TMRC2 IPL TMRC1 IPL Freescale Semiconductor Preliminary 0 0 ...
Page 97
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Register Descriptions 97 ...
Page 98
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SCI0_TIDL SCI0_XMIT IPL IPL 56F8367 Technical Data, Rev TMRA3 IPL TMRA2 IPL TMRA1 IPL IPL Freescale Semiconductor 0 0 Preliminary ...
Page 99
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Register Descriptions 99 ...
Page 100
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 100 PWMA_RL PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL IPL 56F8367 Technical Data, Rev ADCA_CC ADCB_CC IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 101
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Register Descriptions 101 ...
Page 102
... Fast Interrupt Vector Address registers without having jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will 102 VECTOR BASE ADDRESS Part 5.3.1 for details 56F8367 Technical Data, Rev FAST INTERRUPT Freescale Semiconductor Preliminary ...
Page 103
... Fast Interrupt 1 Match Register (FIM1) Base + $ Read Write RESET Figure 5-17 Fast Interrupt 1 Match Register (FIM1) 5.6.15.1 Reserved—Bits 15–7 This bit field is reserved or not implemented read as 0, but cannot be modified by writing. Freescale Semiconductor Preliminary FAST INTERRUPT 0 VECTOR ADDRESS LOW ...
Page 104
... Fast Interrupt 1 defined in the FIM1 register. 5.6.18 IRQ Pending 0 Register (IRQP0) Base + $ Read Write RESET Figure 5-20 IRQ Pending 0 Register (IRQP0) 104 FAST INTERRUPT 1 VECTOR ADDRESS LOW PENDING [16: 56F8367 Technical Data, Rev FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
Page 105
... IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor Preliminary PENDING [32:17] ...
Page 106
... Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–86 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. 106 PENDING [64:49 PENDING [80:65 56F8367 Technical Data, Rev PENDING[85:81 Freescale Semiconductor Preliminary ...
Page 107
... Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. • Required nested exception priority levels are • Required nested exception priority levels are • Required nested exception priority levels are • Required nested exception priority level is 3 Freescale Semiconductor Preliminary VAB INT_DIS ...
Page 108
... Reserved —Base + $1E 5.6.32 Interrupt Priority Register 10 (IPR10) Base + $ Read Write RESET Note: This register is NOT available in the 56F8167 device. 108 FLEXCAN2_ MSGBUF IPL 56F8367 Technical Data, Rev FLEXCAN2_ FLEXCAN2_ FLEXCAN2_ WKUP IPL BOFF IPL ERR IPL Freescale Semiconductor 0 0 Preliminary ...
Page 109
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Register Descriptions 109 ...
Page 110
... IRQs with fixed priorities: • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. 110 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 111
... Software-initiated reset • Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control • System Control Register • Registers for software access to the JTAG ID of the chip Freescale Semiconductor Preliminary 21 clock cycles. 56F8367 Technical Data, Rev. 8 Overview 111 ...
Page 112
... DSP56800E Reference Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR. 112 R/W R Figure 6-1 OMR 56F8367 Technical Data, Rev R/W R/W R/W R/W R Part 4.2 and Part 7 for detailed Freescale Semiconductor 0 MA R/W X Preliminary ...
Page 113
... SIM_CLKOSR Base + $B SIM_GPS Base + $C SIM_PCE Base + $D SIM_ISALH Base + $E SIM_ISALL Base + $F SIM_PCE2 Freescale Semiconductor Preliminary Table 6-1 SIM Registers (SIM_BASE = $00 F350) Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID ...
Page 114
... EMI_ ONCE SW STOP_ MODE EBL0 RST DISABLE 0 0 SWR COPR EXTR POR CTRL JTAG 0 A21 A20 CLKDIS CLKOSEL PWM SCI1 SCI0 SPI1 SPI0 ISAL[23:22 EMI_ ONCE SW STOP_ MODE EBL RST DISABLE DISABLE Freescale Semiconductor 1 0 WAIT_ DISABLE PWM CAN2 0 WAIT_ 0 Preliminary ...
Page 115
... Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this register. Base + $ Read Write RESET Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) Freescale Semiconductor Preliminary ...
Page 116
... This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset). 116 FIELD 56F8367 Technical Data, Rev Freescale Semiconductor Preliminary 0 0 ...
Page 117
... CAN MODE Write RESET Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) 6.5.6.1 Reserved —Bit 15 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.2 PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. Freescale Semiconductor Preliminary ...
Page 118
... SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are for test purposes only, and are subject to significant phase shift at high frequencies. 118 56F8367 Technical Data, Rev. 8 pin and this bit should be SS Freescale Semiconductor Preliminary ...
Page 119
... Selects clock to be muxed out on the CLKO pin. • 00000 = SYS_CLK (from OCCS - DEFAULT) • 00001 = Reserved for factory test—56800E clock • 00010 = Reserved for factory test—XRAM clock • 00011 = Reserved for factory test—PFLASH odd clock Freescale Semiconductor Preliminary Figure ...
Page 120
... SPI inputs/outputs is made in the SIM_GPS register and in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function of GPIOC[3: programmed as decoder functions. This can be changed by altering the appropriate controls in the indicated registers. 120 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 121
... Two Input/Output pins associated with GPIOD can function as GPIO, EMI (default peripheral) or CAN2 (NOT available on the 56F8167 device) signals. GPIO is the default and is enabled/disabled via the GPIOD_PER, as shown in Figure 6-11 peripheral input/output, then the choice between EMI and CAN2 inputs/outputs is made here in the GPS. Freescale Semiconductor Preliminary GPIOC_PER Register GPIO Controlled 0 ...
Page 122
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 122 GPIOD_PER Register GPIO Controlled 0 1 SIM_ GPS Register 0 1 Control Registers 0 0 — — 1 — — 56F8367 Technical Data, Rev. 8 I/O Pad Control 1 Comments EMI CSn pins are always outputs CAN2_TX is always an output CAN2_RX is always an input Freescale Semiconductor Preliminary ...
Page 123
... The Peripheral Clock Enable register is used enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip. Base + $ Read EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC Write RESET Figure 6-13 Peripheral Clock Enable Register (SIM_PCE) Freescale Semiconductor Preliminary TMRB TMRA SCI 1 SCI 56F8367 Technical Data, Rev ...
Page 124
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C Enable (TMRC)—Bit 8 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 124 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 125
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width Modulator A Enable (PWMA)—0 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Register Descriptions 125 ...
Page 126
... Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. 126 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 56F8367 Technical Data, Rev. 8 Instruction Portion ISAL[23:22 Freescale Semiconductor Preliminary 0 1 ...
Page 127
... Power modes permit system and/or peripheral clocks to be disabled when unused. Clock enables provide the means to disable individual clocks. Some peripherals provide further controls to disable unused sub-functions. Refer to Peripheral User Manual for further details. Freescale Semiconductor Preliminary 12 11 ...
Page 128
... External reset 5. Power-on reset Part 6.5.9 and ADC power modes. Power is a function of the system D Q D-FLOP D-FLOP C R Note: Wait disable circuit is similar Reset Figure 6-17 Stop Disable Circuit 56F8367 Technical Data, Rev Table 6-3 Description 56800E STOP_DIS Freescale Semiconductor Preliminary ...
Page 129
... These non-volatile bytes will keep the part secured through reset and through power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 ...
Page 130
... This mechanism completely reases all on-chip Flash, thus disabling Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration (.cfg) files. Add, or uncomment the following configuration command: unlock_flash_on_connect 1 For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual. 130 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 131
... PRDIV8 = FM_CLKDIV[ Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively. 150[kHz] Freescale Semiconductor Preliminary Figure 7-1. FM_CLKDIV[6] will map to the ...
Page 132
... GPIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers will change from port to port. registers. 132 ( ) SYS_CLK (2)(8) < < 200[kHz] (DIV + 1) device (by asserting external chip reset) to return to normal unsecured Table 8-3 defines the actual reset values of these 56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
Page 133
... DEC0 / TMRA 3 pins - Dedicated GPIO 6 pins - EMI CSn pins - SCI1 2 pins - EMI CSn 3 pins -PWMB current sense Freescale Semiconductor Preliminary Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is Peripheral Function Peripheral Function 56F8367 Technical Data, Rev. 8 Configuration ...
Page 134
... Peripheral 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 11 Peripheral 12 Peripheral 13 Peripheral 56F8367 Technical Data, Rev. 8 Reset Function SCI0 EMI Address SPI0 TMRC GPIO EMI Data Functional Signal Package Pin A10 21 A11 22 A12 23 A13 24 A14 25 A15 26 A0 154 Freescale Semiconductor Preliminary ...
Page 135
... Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8167 device GPIO Port GPIOB 1 This is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset. GPIOC Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 1 GPIO 1 1 GPIO ...
Page 136
... Package Pin CS2 / CAN2_TX 55 CS3 / CAN2_RX 56 CS4 57 CS5 58 CS6 59 CS7 60 TXD1 49 RXD1 CS0 CS1 54 ISB0 61 ISB1 63 ISB2 64 TXD0 4 RXD0 SCLK0 146 MOSI0 148 MISO0 147 SS0 145 TC0 133 TC1 135 TD0 129 TD1 130 TD2 131 TD3 132 Freescale Semiconductor Preliminary ...
Page 137
... Pins in italics are NOT available in the 56F8167 device GPIO Port GPIOF 1. See Part 6.5.8 to determine how to select peripherals from this set Part 9 Joint Test Action Group (JTAG) 9.1 56F8367 Information Please contact your Freescale device/package-specific BSDL information. Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 Peripheral 1 Peripheral 2 Peripheral 3 Peripheral ...
Page 138
... However, normal precautions are advised to avoid application maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. 138 are stress ratings only, and functional operation at the maximum CAUTION of any voltages higher 56F8367 Technical Data, Rev. 8 than Freescale Semiconductor Preliminary ...
Page 139
... Pin Group 7: CLKO, WR, RD Pin Group 8: PWMA0-5, PWMB0-5 Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST, TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3 Pin Group 10: TCK Pin Group 11: XTAL, EXTAL Pin Group 12: ANA0-7, ANB0-7 Pin Group 13: OCR_DIS, CLKMODE Freescale Semiconductor Preliminary ( SSA_ADC Symbol ...
Page 140
... Technical Data, Rev. 8 Typ Max Unit — — V — — V — — Value Value Unit 160-pin LQFP 160MAPBGA 38.5 39.90 °C/W 35.4 46.8 °C/W 33 TBD °C/W 31.5 TBD °C/W 8.6 TBD °C/W 0.8 TBD °C/W User-determined I/O W θ 7 ( Freescale Semiconductor Notes Preliminary ...
Page 141
... Ambient Operating Temperature (Industrial) Flash Endurance (Automotive) (Program Erase Cycles) Flash Endurance (Industrial) (Program Erase Cycles) Flash Data Retention Note: Total chip source or sink current cannot exceed 200mA See Pin Groups in Table 10-1. Freescale Semiconductor Preliminary = SSA_ADC , DDA DDA_ADC Symbol ...
Page 142
... μA 0 +/- μA -500 μA 0 +/- 2 μA 0 +/- 2 μA 0 +/- 2 μA 0 +/- μA 0 +/- 2 DDA μA 0 +/- 2 DDA μA — 200 DDA μA 0 +/- 2 3.0V to OUT 5. — — V — — pF — — — pF — 6 — — pF Freescale Semiconductor Preliminary DDA DDA ...
Page 143
... On-Chip Regulator Enabled (OCR_DIS = Low) 1 Mode I DD_IO RUN1_MAC 155mA Wait3 91mA Stop1 6mA Stop2 5.1mA 1. No Output Switching 2. Includes Processor Core current supplied by internal voltage regulator Freescale Semiconductor Preliminary Symbol Min 1.75 POR — V EI2.5 V — EI3.3 I — bias , an interrupt is generated. ...
Page 144
... ADC powered off • PLL powered off • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off Typical Max Unit — 2.75 V — 2.75 V — 2.75 V — 700 mA 5 μ — 30 minutes Freescale Semiconductor Preliminary ...
Page 145
... The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at FMOPT0 and FMOPT1. 3. See Application Note, AN1980, for methods to increase accuracy. 4. Assuming a 12-bit range from 0V to 3.3V. 5. Typical resolution calculated using equation, Freescale Semiconductor Preliminary Table 10-10. PLL Parameters Symbol Min T 0 ...
Page 146
... Figure 10-2 Signal States Symbol Min 20 T prog 20 T erase 100 T me 56F8367 Technical Data, Rev. 8 10-5. Unless otherwise specified, High 90% 50% 10% Rise Time and Data3 Valid Data3 Data Active Typ Max Unit — — μs — — ms — — ms Freescale Semiconductor Preliminary ...
Page 147
... The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f the 56F8300 Peripheral User Manual. 3. This is the minimum time required after the PLL set up is changed to ensure reliable operation. Freescale Semiconductor Preliminary Symbol Min ...
Page 148
... EMI chapter of 56F8367 Technical Data, Rev. 8 Typ Max Unit 0. — 120 ohms — 250 ps — 1.5 ns — 300 ps — 300 ps μA 250 290 μA 80 110 μ Figure 10-4 10-16. Freescale Semiconductor Preliminary ...
Page 149
... Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 10-4 External Memory Interface Timing Note: When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. Freescale Semiconductor Preliminary t ARDD t ...
Page 150
... DCAOE WWS,WWSS 0.50 0.25 + DCAEO WWSH 0.00 RWSH 1.00 RWSS,RWS 1 — N/A 1.00 RWS 1.00 RWSS,RWS 0.00 RWSS 1.00 RWSS,RWS WWSH,RWSS 0.25 + DCAEO RWSS,RWSH 2 0. MDAR 0.75 + DCAEO WWSS, WWSH 1.00 0.50 RWSH, WWSS, 3 MDAR 0.75 + DCAOE Freescale Semiconductor Preliminary Unit ...
Page 151
... The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. The interrupt instruction fetch is visible on the pins only in Mode 3. Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing ...
Page 152
... WR t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 10-7 External Level-Sensitive Interrupt Timing 152 IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O 56F8367 Technical Data, Rev RDA First Fetch First Fetch Freescale Semiconductor Preliminary ...
Page 153
... Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Freescale Semiconductor Preliminary t IRI Table 10-18 SPI Timing Symbol Min ELD — ...
Page 154
... Freescale Semiconductor 10-13 10-13 10-13 10-13 10-13 Preliminary ...
Page 155
... SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-11 SPI Master Timing (CPHA = 1) Freescale Semiconductor Preliminary SS is held High on master MSB in Bits 14– Master MSB out Bits 14– ...
Page 156
... Figure 10-13 SPI Slave Timing (CPHA = 1) 156 ELD Slave MSB out Bits 14– MSB in Bits 14– ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F8367 Technical Data, Rev ELG Slave LSB out t DI LSB ELG Slave LSB out LSB in Freescale Semiconductor t DI Preliminary ...
Page 157
... Table 10-20 Quadrature Decoder Timing Characteristic Quadrature input period Quadrature input high / low period Quadrature phase period 1. In the formulas listed the clock cycle. For 60MHz operation, T=16.67ns. 2. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary Table 10-19 Timer Timing Symbol Min ...
Page 158
... Table 10-21 SCI Timing Min BR — 0.965/BR PW 0.965/BR PW RXD PW Figure 10-16 RXD Pulse Width TXD PW Figure 10-17 TXD Pulse Width 56F8367 Technical Data, Rev Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns 10-16 1.04/BR ns 10-17 Freescale Semiconductor Preliminary ...
Page 159
... TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time 1. TCK frequency of operation must be less than 1/8 the processor rate processor clock period (nominally 1/60MHz) Freescale Semiconductor Preliminary Table 10-22 CAN Timing Symbol Min — ...
Page 160
... TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-20 Test Access Port Timing Diagram TRST (Input) 160 1 )/ Input Data Valid TRST Figure 10-21 TRST Timing Diagram 56F8367 Technical Data, Rev Output Data Valid Output Data Valid Freescale Semiconductor Preliminary ...
Page 161
... ADC A current ADC B current Quiescent current Uncalibrated Gain Error (ideal = 1) Uncalibrated Offset Voltage 6 Calibrated Absolute Error 7 Calibration Factor 1 Calibration Factor 2 Crosstalk between channels Common Mode Voltage Signal-to-noise ratio Freescale Semiconductor Preliminary Table 10-24 ADC Parameters Symbol Min V V ADIN REFL INL — ...
Page 162
... Please see the 56F8300Peripheral User’s Manual for additional information on ADC calibration. 8. ENOB = (SINAD - 1.76)/6.02 162 Symbol Min SINAD — THD — SFDR — ENOB — .9V in REFH 56F8367 Technical Data, Rev. 8 Typ Max Unit 59.1 — db 60.6 — db 61.1 — db 9.6 — Bits Freescale Semiconductor Preliminary ...
Page 163
... Although not guaranteed believed that calibration will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes. Freescale Semiconductor Preliminary = 0.60V and 2.70V in 56F8367 Technical Data, Rev ...
Page 164
... These include RAM, Flash memory and the ADCs. 164 / 2, while the other charges to the analog input voltage. When the REFH REFH REFH 56F8367 Technical Data, Rev The switches switch REFH REFH 1pF Freescale Semiconductor Preliminary ...
Page 165
... For instance, if there is a total of 8 PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. Freescale Semiconductor Preliminary 2 *F CMOS power dissipation corresponding to the Intercept 1 ...
Page 166
... ANB4 ANB3 121 ANB2 ANB1 ANB0 V SSA_ADC V DDA_ADC V REFH V REFP V REFMID V REFN V REFLO TEMP_SENSE ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO V DD_IO V 3 CAP EXTAL XTAL VDDA_OSC_PLL OCR_DIS FAULTA3 D3 FAULTA2 FAULTA1 81 D2 FAULTA0 PWMA5 Freescale Semiconductor Preliminary ...
Page 167
... A10 61 22 A11 62 23 A12 63 24 A13 64 25 A14 65 * When the on-chip regulator is disabled, these four pins become 2.5V V Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name V 81 PWMA5 FAULTA0 DD_IO PWMB3 83 D2 PWMB4 84 FAULTA1 PWMB5 85 FAULTA2 GPIOB5 86 D3 GPIOB6 87 FAULTA3 ...
Page 168
... ANB4 SS 56F8367 Technical Data, Rev. 8 Pin No. Signal Name 146 SCLK0 147 MISO0 148 MOSI0 149 D11 150 D12 151 D13 152 D14 153 D15 154 A0 155 PHASEA0 156 PHASEB0 157 INDEX0 158 HOME0 159 EMI_MODE 160 V SS Freescale Semiconductor Preliminary ...
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... A15 GPIOB0 GPIOB2 GPIOB1 M GPIOB3 GPIOB4 GPIOB7 PWMB5 N PWMB0 PWMB2 PWMB3 GPIOB5 P PWMB1 PWMB4 GPIOB6 TXD1 Figure 11-2 Top View, 56F8367 160-Pin MAPBGA Package Freescale Semiconductor Preliminary D12 V 1 D11 SCLK0 TMS PP D13 MOSI0 CAN_RX TDI D14 SS0 CAN_TX TDO TCK ...
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... Signal Name No. A13 ANB5 B12 ANB6 A12 ANB7 B11 EXTBOOT J11 V SS A11 ISA0 C11 ISA1 D11 ISA2 B10 TD0 A10 TD1 D10 TD2 E10 TD3 A9 TC0 F11 V DD_IO B9 TC1 D9 TRST D8 TCK A8 TMS B8 TDI D7 TDO CAN_TX B7 CAN_RX CAP D5 SS0 . Freescale Semiconductor Preliminary ...
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... L2 GPIOB2 P12 M1 GPIOB3 N11 M2 GPIOB4 E9 N1 PWMB0 M12 P1 PWMB1 P13 N2 PWMB2 E7 Please see http://www.freescale.com for the most current mechanical drawing. Freescale Semiconductor Preliminary Ball Signal Name No. No. IRQB G14 ANA6 FAULTB0 E13 ANA7 FAULTB1 E11 TEMP_SENSE FAULTB2 E12 V D0 F14 ...
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... BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS DIM MIN MAX A 1.32 1.75 A1 0.27 0.47 A2 1.18 REF b 0.35 0.65 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC 5 0. 160X DETAIL K ° ROTATED 90 CLOCKWISE Freescale Semiconductor Preliminary ...
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... GPIOB4 PWMB0 41 PWMB1 PWMB2 * When the on-chip regulator is disabled, these four pins become 2.5V V Figure 11-4 Top View, 56F8167 160-Pin LQFP Package Freescale Semiconductor Preliminary Figure 11-4 shows the package outline for the 160-pin LQFP, . DD_CORE 56F8367 Technical Data, Rev. 8 56F8167 Package and Pin-Out Information ...
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... GPIOC8 127 GPIOC9 128 GPIOC10 129 GPIOE10 130 GPIOE11 131 GPIOE12 132 GPIOE13 133 TC0 134 V DD_IO 3* 135 TC1 136 TRST 137 TCK 138 TMS 139 TDI 140 TDO 141 142 NC 143 NC 144 V 2* CAP 145 SS0 Freescale Semiconductor Preliminary ...
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... D10 72 33 GPIOB0 73 34 GPIOB1 74 35 GPIOB2 75 36 GPIOB3 76 37 GPIOB4 77 38 PWMB0 78 39 PWMB1 79 40 PWMB2 80 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name IRQB 106 ANA6 FAULTB0 107 ANA7 FAULTB1 108 NC FAULTB2 109 V REFLO D0 110 V REFN D1 111 V REFMID FAULTB3 ...
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... D 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 24.00 BSC L 0.45 0.75 L1 1.00 REF R1 0.08 --- R2 0.08 0.20 S 0.20 --- ° ° θ ° θ --- ° ° θ ° ° θ Freescale Semiconductor Preliminary ...
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... D where Thermocouple temperature on top of package ( T Ψ = Thermal characterization parameter ( Power dissipation in package (W) D Freescale Semiconductor Preliminary , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with a JT ...
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... SS /V Ceramic and tantalum capacitors tend to provide better DDA SSA. layers of the PCB with approximately 100μF, preferably with a high-grade 56F8367 Technical Data, Rev. 8 higher than pin on the hybrid controller, and DD and V (GND and Freescale Semiconductor Preliminary ...
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... Flash, RAM and internal logic are powered from the core regulator output • and V 2 are not connected in the customer system PP PP • All circuitry, analog and digital, shares a common V V DDA_OSC_PLL REG OSC Freescale Semiconductor Preliminary , V REF DDA pins. bus CAP REG ...
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... Technical Data, Rev. 8 Ambient Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8367VPY60 40 -40° 105° C MC56F8167VPY 60 -40° 105° C MC56F8367VPYE* 60 -40° 125° C MC56F8367MPYE* 40 -40° 105° C MC56F8167VPYE* 60 -40° 105° C MC56F8367VVF* Freescale Semiconductor Preliminary ...
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... Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Power Distribution and I/O Ring Implementation 181 ...
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... Technical Data, Rev. 8 Freescale Semiconductor Preliminary ...
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... Freescale Semiconductor Preliminary 56F8367 Technical Data, Rev. 8 Power Distribution and I/O Ring Implementation 183 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...