MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet
MC56F8147VPYE
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MC56F8147VPYE Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8347 Rev.11 01/2007 freescale.com ...
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... Section 12.3. Table 10-1; also removed overall life Table 10-4. Table 13-1. Table 10-4 and additional minor edits Table 10-4. Table Table 10-14 by increasing maximum Table 2-2. Table 2-2: Table 2- the design used in a debugging SS Freescale Semiconductor Preliminary D 2-2. ...
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... SPI0 or SCI1 or SCI0 or GPIOE GPIOD GPIOE 4 2 Freescale Semiconductor Preliminary • Four 4-channel, 12-bit ADCs • Temperature Sensor • two Quadrature Decoders • FlexCAN module • Two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interfaces (SPIs) • four general-purpose Quad Timers • ...
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... Information . . . . . . . . . . . . . . . . . 156 11.2. 56F8147 Package and Pin-Out Information . . . . . . . . . . . . . . . . . 163 Part 12: Design Considerations . . . . . . . . 167 12.1. Thermal Design Considerations . . . . . . . . 167 12.2. Electrical Design Considerations . . . . . . . 168 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . . 169 Part 13: Ordering Information . . . . . . . . . . 170 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
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... Table 1-1 outlines the key differences between the 56F8347 and 56F8147 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quad Timer Quadrature Decoder Temperature Sensor Dedicated GPIO Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8347 60MHz/60 MIPS 4KB 8KB — ...
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... In the 56F8147, two general-purpose Quad Timers; Timer A works in conjunction with Quadrature Decoder 0 or GPIO and Timer C works in conjunction with GPIO • FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive 6 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
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... The 56F8347 and 56F8147 support program execution from internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Device Description ...
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... Data RAM. It also supports program execution from external memory. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program Flash memory area, which can be independently 8 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
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... A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Award-Winning Development Environment ...
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... The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User’s Manual for clarification on the operation of all three of these peripherals. 10 Figure 1-1 and Figure 56F8347 Technical Data, Rev.11 1-2. Figure 1-1 illustrates how the Part 2, Signal/Connection Freescale Semiconductor Preliminary ...
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... Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are Freescale Semiconductor Preliminary JTAG / EOnCE pdb_m[15:0} ...
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... SIM COP Reset COP 2 FlexCAN 13 PWMA SYNC Output 13 PWMB SYNC Output ch3i ch2i 2 Timer C ch3o ch2o 8 ADCB 8 ADCA 1 TEMP_SENSE Note: ADCA and ADCB use the same volt- age reference circuit with V REFH and V pins. REFMID REFN REFLO Freescale Semiconductor , V REFP Preliminary ...
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... Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. Freescale Semiconductor Preliminary Table 1-2 Bus Signal Names Function ...
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... Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 14 Freescale Literature Distribution Table 1-3 Chip Documentation Description Logic State Signal State True False True False 56F8347 Technical Data, Rev.11 Centers, or online Order Number DSP56800ERM MC56F8300UM MC56F83xxBLUM MC56F8347 MC56F8347E MC56F8147E 1 Voltage Asserted Deasserted Asserted Deasserted Freescale Semiconductor Preliminary at ...
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... Temperature Sense Dedicated GPIO 1. If the on-chip regulator is disabled, the V 2. Alternately, can function as Quad Timer pins 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO Freescale Semiconductor Preliminary Figure 2-2. In Table 2-2, each table row describes the signal or signals 2 pins serve as 2 ...
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... Technical Data, Rev.11 Quadrature Decoder 0 or Quad Timer A SPI0 or GPIO Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO PWMA PWMB ADCA REF ADCB Temperature Sense Diode FlexCAN Quad Timer C and D or GPIO INTERRUPT/ PROGRAM CONTROL 1 (160-pin LQFP) Freescale Semiconductor Preliminary ...
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... SCI 1 RXD1 (GPIOD7) or GPIO JTAG/ EOnCE Port * When the on-chip regulator is disabled, these four pins become 2.5V V DD_CORE Figure 2-2 56F8147 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. Freescale Semiconductor Preliminary V DD_IO DDA_ADC ...
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... Oscillator and PLL Power — This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. 56F8347 Technical Data, Rev.11 Table 2-2. Please contact Signal Description Freescale Semiconductor Preliminary ...
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... V 1 141 CLKMODE 99 H12 EXTAL 94 J12 Freescale Semiconductor Preliminary State Type During Reset Supply V — These pins provide ground for chip logic and I/O SS drivers. Supply ADC Analog Ground — This pin supplies an analog ground to the ADC modules. Input Input On-Chip Regulator Disable — ...
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... After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA8, clear bit 8 in the GPIOA_PUR register. 56F8347 Technical Data, Rev.11 Signal Description for details. Freescale Semiconductor Preliminary ...
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... A13 24 J1 (GPIOA5) A14 25 J2 (GPIOA6) A15 26 J3 (GPIOA7) Freescale Semiconductor Preliminary State Type During Reset Output In reset, Address Bus — specify two of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus ...
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... In these cases, the GPIO_B_PER can be used to individually disable the GPIO. The CLKOSR register in the SIM ( see Part 6.5.7) can then be used to choose between address and clock functions. 56F8347 Technical Data, Rev.11 Signal Description Table 4-4 for Freescale Semiconductor Preliminary ...
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... L13 (GPIOF12 L14 (GPIOF13 L12 (GPIOF14 L11 (GPIOF15) Freescale Semiconductor Preliminary State Type During Reset Input/ In reset, Data Bus — specify part of the data for external Output output is program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control enabled register (BCR), D0– ...
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... RD is tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register. 56F8347 Technical Data, Rev.11 Signal Description Freescale Semiconductor Preliminary ...
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... (CS0) (GPIOD8 (CS1) (GPIOD9) Freescale Semiconductor Preliminary State Type During Reset Output In reset, Write Enable — asserted during external memory output is write cycles. When WR is asserted low, pins D0 - D15 disabled, become outputs and the device puts data on the bus. When pull-up is ...
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... Port E GPIO — This GPIO pin can be individually Output programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOE_PUR register. 56F8347 Technical Data, Rev.11 Signal Description Freescale Semiconductor Preliminary ...
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... N5 (GPIOD7) TCK 137 D8 TMS 138 A8 TDI 139 B8 TDO 140 D7 Freescale Semiconductor Preliminary State Type During Reset Output In reset, Transmit Data — SCI1 transmit data output output is Input/ disabled, Port D GPIO — This GPIO pin can be individually Output pull-up is programmed as an input or output pin. ...
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... Port C GPIO — This GPIO pin can be individually Input/ programmed as an input or output pin. Output After reset, the default state is PHASEB0. To deactivate the internal pull-up resistor, clear bit 5 of the GPIOC_PUR register. 56F8347 Technical Data, Rev.11 Signal Description . If SS Freescale Semiconductor Preliminary ...
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... Signal Name No. No. INDEX0 157 A1 (TA2) (GPOPC6) HOME0 158 B3 (TA3) (GPIOC7) SCLK0 146 A6 (GPIOE4) Freescale Semiconductor Preliminary State Type During Reset Schmitt Input, Index — Quadrature Decoder 0, INDEX input Input pull-up enabled Schmitt TA2 — Timer A, Channel 2 Input/ Output Schmitt Port C GPIO — This GPIO pin can be individually Input/ programmed as an input or output pin ...
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... Input/ Port E GPIO — This GPIO pin can be individually Output programmed as input or output pin. After reset, the default state is SS0. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOE_PUR register. 56F8347 Technical Data, Rev.11 Signal Description Freescale Semiconductor Preliminary ...
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... Ball Signal Name No. No. PHASEA1 6 C1 (TB0) (SCLK1) (GPIOC0) PHASEB1 7 D1 (TB1) (MOSI1) (GPIOC1) Freescale Semiconductor Preliminary State Type During Reset Schmitt Input, Phase A1 — Quadrature Decoder 1, PHASEA input for Input pull-up decoder 1. enabled Schmitt TB0 — Timer B, Channel 0 Input/ Output Schmitt SPI 1 Serial Clock — ...
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... In the 56F8347, the default state after reset is HOME1. In the 56F8147, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 3 in the GPIOC_PUR register. 56F8347 Technical Data, Rev.11 Signal Description Part 6.5.8. Freescale Semiconductor Preliminary ...
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... PWMB1 39 P1 PWMB2 40 N2 PWMB3 43 N3 PWMB4 44 P2 PWMB5 45 M3 Freescale Semiconductor Preliminary State Type During Reset Output In reset, PWMA0 - 5 — These are six PWMA outputs. output is disabled, pull-up is enabled Schmitt Input, ISA0 - 2 — These three input current status pins are used for ...
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... Connect to a 0.1μF low ESR capacitor. Input Analog V — Analog Reference Voltage Low. This should REFLO Input normally be connected to a low-noise V 56F8347 Technical Data, Rev.11 Signal Description Part 6.5.8. must be REFH DDA_ADC. & V — Internal pins for voltage REFN . SS Freescale Semiconductor Preliminary ...
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... E11 SENSE CAN_RX 143 B7 CAN_TX 142 D6 TC0 133 A9 (GPIOE8) TC1 135 B9 (GPIOE9) Freescale Semiconductor Preliminary State Type During Reset Input Analog ANB0 - 3 — Analog inputs to ADC B, channel 0 Input Input Analog ANB4 - 7 — Analog inputs to ADC B, channel 1 Input Output Analog Temperature Sense Diode — This signal connects to an ...
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... To deactivate the internal pull-up resistor, set the RESET bit in the SIM_PUDR register. See Output Output Reset Output — This output reflects the internal reset state of the chip. 56F8347 Technical Data, Rev.11 Signal Description Part 6.5.6 Part 6.5.6 for details. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...
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... Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. EXTBOOT 124 B11 EMI_MODE 159 B2 Freescale Semiconductor Preliminary State Type During Reset Schmitt Input, External Boot — This input is tied to V Input pull-up to boot from off-chip memory (assuming that the on-chip enabled Flash memory is not in a secure state) ...
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... Detector Figure 3-1 OCCS Block Diagram Table 10-15. A recommended crystal oscillator circuit is shown 56F8347 Technical Data, Rev.11 Figure 3-1 shows the ZSRC SYS_CLK2 Source to SIM PLLCOD Postscaler Postscaler CLK ÷ 1,2,4,8 Bus Interface LCK Loss of Reference Clock Interrupt Freescale Semiconductor Preliminary ...
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... The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User’s Manual. Freescale Semiconductor Preliminary EXTAL XTAL Sample External Crystal Parameters: ...
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... Erase/Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously — None 8KB None 8KB Erase/Program via Flash Interface unit and word to CDBW 56F8347 Technical Data, Rev.11 Figure 3-4. The external clock Use Restrictions Freescale Semiconductor Preliminary ...
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... The EMI_MODE pin also affects the reset vector address, as provided in be configured as address or chip select signals to access addresses at P:$10 0000 and above. Note: Program RAM is NOT available on the 56F8147 device. Freescale Semiconductor Preliminary Table 4-3. Changing the OMR MB bit will have no Chip Operating Mode Mode 0 – ...
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... External Program RAM COP Reset Address = 00 0002 Boot Location = 00 0000 at boot up. DD 56F8347 Technical Data, Rev.11 1 Mode 1 ( External Boot EMI_MODE = 1 20-Bit External Address Bus 5 External Program Memory External Program RAM COP Reset Address = 02 0002 6 Boot Location = 02 0000 Part 7. Freescale Semiconductor Preliminary 5 Part ...
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... FLEXCAN 27 0-2 FLEXCAN 28 0-2 FLEXCAN 29 0-2 GPIOF 30 0-2 GPIOE 31 0-2 Freescale Semiconductor Preliminary Vector Base Address + Reserved for Reset Overlay Reserved for COP Reset Overlay P:$04 Illegal Instruction P:$06 SW Interrupt 3 P:$08 HW Stack Overflow P:$0A Misaligned Long Word Access P:$0C OnCE Step Counter ...
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... Timer C, Channel 1 P:$74 Timer C, Channel 2 P:$76 Timer C, Channel 3 P:$78 Timer B, Channel 0 P:$7A Timer B, Channel 1 P:$7C Timer B, Channel 2 P:$7E Timer B, Channel 3 P:$80 Timer A, Channel 0 P:$82 Timer A, Channel 1 P:$84 Timer A, Channel 2 P:$86 Timer A, Channel 3 56F8347 Technical Data, Rev.11 1 (Continued) Interrupt Function Freescale Semiconductor Preliminary ...
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... On-Chip Data RAM X:$00 0000 3 8KB 1. All addresses are 16-bit Word addresses, not byte addresses the Operating Mode Register (OMR). 3. The Data RAM is organized 32-bit memory to allow single-cycle long-word operations. Freescale Semiconductor Preliminary Vector Base Address + P:$88 SCI 0 Transmitter Empty P:$8A ...
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... Technical Data, Rev.11 Data Memory FM_BASE + $14 Banked Registers Unbanked Registers FM_BASE + $00 8KB Note: Data Flash is NOT available in the 56F8147 device. Sector Size Page Size bits 512 x 16 bits 256 x 16 bits 256 x 16 bits bits 256 x 16 bits Freescale Semiconductor Preliminary ...
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... OCR (bits) X:$FF FFFC OCLSR (8 bits) X:$FF FFFD OTXRXSR (8 bits) X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFF OTX1 / ORX1 Freescale Semiconductor Preliminary Table 4-8 EOnCE Memory Map Reserved External Signal Control Register Reserved Breakpoint Unit [0] Counter Reserved Breakpoint 1 Unit [0] Mask Register ...
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... X:$00 F310 GPIOD X:$00 F320 GPIOE X:$00 F330 56F8347 Technical Data, Rev.11 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 Freescale Semiconductor Preliminary ...
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... CSBAR 4 $4 CSBAR 5 $5 CSBAR 6 $6 CSBAR 7 $7 CSOR 0 $8 CSOR 1 $9 CSOR 2 $A CSOR 3 $B Freescale Semiconductor Preliminary Prefix Base Address GPIOF X:$00 F340 SIM X:$00 F350 LVI X:$00 F360 FM X:$00 F400 FC X:$00 F800 (EMI_BASE = $00 F020) Register Description Chip Select Base Address Register 0 ...
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... Comparator Load Register 2 $A Comparator Status and Control Register Reserve $10 Compare Register 1 $11 Compare Register 2 $12 Capture Register $13 Load Register 56F8347 Technical Data, Rev.11 Reset Value 0x016B sets the default number of wait states to 11 for both read and write accesses Freescale Semiconductor Preliminary ...
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... TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSC Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description $14 Hold Register $15 Counter Register $16 Control Register $17 Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 ...
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... Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A Comparator Status and Control Register Reserved $20 Compare Register 1 $21 Compare Register 2 $22 Capture Register $23 Load Register $24 Hold Register $25 Counter Register $26 Control Register 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
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... Table 4-13 Quad Timer C Registers Address Map Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 Freescale Semiconductor Preliminary (TMRB_BASE = $00 F080) Address Offset $27 Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 ...
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... Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register $35 Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register 56F8347 Technical Data, Rev.11 Register Description Freescale Semiconductor Preliminary ...
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... TMRD1_CMP2 TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR Freescale Semiconductor Preliminary (TMRD_BASE = $00 F100) Address Offset $0 Compare Register 1 $1 Compare Register 2 $2 Capture Register $3 Load Register $4 Hold Register $5 Counter Register $6 Control Register ...
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... Fault Status Acknowledge Register $3 Output Control Register $4 Counter Register $5 Counter Modulo Register $6 Value Register 0 $7 Value Register 1 $8 Value Register 2 $9 Value Register 3 $A Value Register 4 $B Value Register 5 $C Dead Time Register 56F8347 Technical Data, Rev.11 Register Description Register Description Freescale Semiconductor Preliminary ...
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... PWMB_PMCNT PWMB_PWMCM PWMB_PWMVAL0 PWMB_PWMVAL1 PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Freescale Semiconductor Preliminary (PWMA_BASE = $00 F140) Address Offset $D Disable Mapping Register 1 $E Disable Mapping Register 2 $F Configure Register $10 Channel Control Register $11 Port Register $12 PWM Internal Correction Control Register ...
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... Position Difference Counter Hold Register $5 Revolution Counter Register $6 Revolution Hold Register $7 Upper Position Counter Register $8 Lower Position Counter Register $9 Upper Position Hold Register $A Lower Position Hold Register $B Upper Initialization Register $C Lower Initialization Register $D Input Monitor Register 56F8347 Technical Data, Rev.11 Register Description Freescale Semiconductor Preliminary ...
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... IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 ICTL Table 4-20 Analog-to-Digital Converter Registers Address Map Register Acronym ADCA_CR 1 ADCA_CR 2 ADCA_ZCC Freescale Semiconductor Preliminary (ITCN_BASE = $00 F1A0) Address Offset $0 Interrupt Priority Register 0 $1 Interrupt Priority Register 1 $2 Interrupt Priority Register 2 $3 Interrupt Priority Register 3 ...
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... High Limit Register 3 $1D High Limit Register 4 $1E High Limit Register 5 $1F High Limit Register 6 $20 High Limit Register 7 $21 Offset Register 0 $22 Offset Register 1 $23 Offset Register 2 $24 Offset Register 3 $25 Offset Register 4 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
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... ADCB_RSLT 2 ADCB_RSLT 3 ADCB_RSLT 4 ADCB_RSLT 5 ADCB_RSLT 6 ADCB_RSLT 7 ADCB_LLMT 0 ADCB_LLMT 1 ADCB_LLMT 2 ADCB_LLMT 3 ADCB_LLMT 4 ADCB_LLMT 5 ADCB_LLMT 6 ADCB_LLMT 7 ADCB_HLMT 0 Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $26 Offset Register 5 $27 Offset Register 6 $28 Offset Register 7 $29 Power Control Register $2A ADC Calibration Register (ADCB_BASE = $00 F240) ...
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... Offset Register 7 $29 Power Control Register $2A ADC Calibration Register (TSENSOR_BASE = $00 F270) Address Offset Register Description $0 Control Register (SCI0_BASE = $00 F280) Address Offset $0 Baud Rate Register $1 Control Register Reserved $3 Status Register $4 Data Register 56F8347 Technical Data, Rev.11 Register Description Register Description Freescale Semiconductor Preliminary ...
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... Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Table 4-27 Computer Operating Properly Registers Address Map Register Acronym COPCTL COPTO COPCTR Freescale Semiconductor Preliminary (SCI1_BASE = $00 F290) Address Offset $0 Baud Rate Register $1 Control Register Reserved $3 Status Register ...
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... Interrupt Pending Register $8 Interrupt Edge-Sensitive Register $9 Push-Pull Mode Register $A Raw Data Input Register 56F8347 Technical Data, Rev.11 Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF — Freescale Semiconductor Preliminary ...
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... GPIOC_DR $1 GPIOC_DDR $2 GPIOC_PER $3 GPIOC_IAR $4 GPIOC_IENR $5 GPIOC_IPOLR $6 GPIOC_IPR $7 GPIOC_IESR $8 GPIOC_PPMODE $9 GPIOC_RAWDATA $A Freescale Semiconductor Preliminary (GPIOB_BASE = $00 F300) Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 Interrupt Enable Register $6 Interrupt Polarity Register $7 Interrupt Pending Register $8 Interrupt Edge-Sensitive Register ...
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... Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF — Freescale Semiconductor Preliminary ...
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... Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL Freescale Semiconductor Preliminary (GPIOF_BASE = $00 F340) Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 Interrupt Enable Register ...
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... Hot temperature ADC reading of Temperature Sensor; value set during factory test $1B 16-Bit Information Option Register 1 Not used $1C 16-Bit Information Option Register 2 Room temperature ADC reading of Temperature Sensor; value set during factory test 56F8347 Technical Data, Rev.11 Register Description Freescale Semiconductor Preliminary ...
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... FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $0 Module Configuration Register Reserved $3 Control Register 0 Register $4 Control Register 1 Register $5 Free-Running Timer Register $6 Maximum Message Buffer Configuration Register ...
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... Message Buffer 4 ID Low Register $63 Message Buffer 4 Data Register $64 Message Buffer 4 Data Register $65 Message Buffer 4 Data Register $66 Message Buffer 4 Data Register Reserved $68 Message Buffer 5 Control / Status Register $69 Message Buffer 5 ID High Register $6A Message Buffer 5 ID Low Register 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
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... FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $6B Message Buffer 5 Data Register $6C Message Buffer 5 Data Register $6D Message Buffer 5 Data Register $6E Message Buffer 5 Data Register Reserved $70 ...
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... Message Buffer 12 ID Low Register $A3 Message Buffer 12 Data Register $A4 Message Buffer 12 Data Register $A5 Message Buffer 12 Data Register $A6 Message Buffer 12 Data Register Reserved $A8 Message Buffer 13 Control / Status Register $A9 Message Buffer 13 ID High Register $AA Message Buffer 13 ID Low Register 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
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... Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the Boot Flash memory. Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset ...
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... Table 5-1 Interrupt Mask Bit Definition 1 SR[9] SR[ Core status register bits indicating current interrupt mask within the core. 74 4-5, Interrupt Vector Table Contents. 1 Permitted Exceptions 0 Priorities Priorities Priorities Priority 3 56F8347 Technical Data, Rev.11 Masked Exceptions None Priority 0 Priorities 0, 1 Priorities Freescale Semiconductor Preliminary ...
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... FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. Freescale Semiconductor Preliminary Current Interrupt Priority 1 ...
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... The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. 76 any0 Level 0 82 -> Priority Encoder any3 Level 3 IACK 82 -> Priority Encoder 56F8347 Technical Data, Rev.11 INT VAB CONTROL IPIC SR[9:8] PIC_EN Freescale Semiconductor Preliminary ...
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... IRQP1 $12 IRQP2 $13 IRQP3 $14 IRQP4 $15 IRQP5 $16 ICTL $1D Freescale Semiconductor Preliminary Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 ...
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... ADCB_CC IPL FAST INTERRUPT FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT FAST INTERRUPT 1 VECTOR ADDRESS HIGH IRQB IRQA 1 IRQB STATE STATE INT_DIS EDG Freescale Semiconductor TRBUF IPL IRQA IPL 0 0 GPIOC IPL TMRC1 IPL TMRA1 IPL 1 PEND- 1 ING [81] IRQA EDG Preliminary ...
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... IRQ is priority level 2 • IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1) Freescale Semiconductor Preliminary STPCNT IPL ...
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... IRQ is priority level 2 • IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 Interrupt Priority Register 2 (IPR2 FMERR IPL LOCK IPL LVI IPL 56F8347 Technical Data, Rev. IRQB IPL IRQA IPL Freescale Semiconductor Preliminary 0 0 ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Register Descriptions 81 ...
Page 82
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level GPIOF FCMSGBUF IPL FCWKUP IPL IPL 56F8347 Technical Data, Rev. FCERR IPL FCBOFF IPL Freescale Semiconductor Preliminary ...
Page 83
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Register Descriptions 83 ...
Page 84
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SPI1_RCV IPL IPL 56F8347 Technical Data, Rev. GPIOA GPIOB GPIOC IPL IPL IPL Freescale Semiconductor Preliminary ...
Page 85
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Register Descriptions 85 ...
Page 86
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SCI1_RCV SCI1_RERR IPL IPL IPL 56F8347 Technical Data, Rev. SCI1_TIDL SCI1_XMIT SPI0_XMIT IPL IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 87
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Register Descriptions 87 ...
Page 88
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level TMRD2 IPL TMRD1 IPL TMRD0 IPL 56F8347 Technical Data, Rev. DEC0_XIRQ DEC0_HIRQ IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 89
... IRQ is priority level 1 • IRQ is priority level 2 5.6.8 Interrupt Priority Register 7 (IPR7) Base + $ Read TMRA0 IPL TMRB3 IPL Write RESET Figure 5-10 Interrupt Priority Register (IPR7) Freescale Semiconductor Preliminary TMRB2 IPL TMRB1 IPL TMRB0 IPL 56F8347 Technical Data, Rev.11 Register Descriptions ...
Page 90
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 90 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 91
... SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary SCI0_TIDL ...
Page 92
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 92 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 93
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary PWMA_RL PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL ...
Page 94
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 94 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 95
... The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting the full VAB to the 56800E core; see Freescale Semiconductor Preliminary 12 11 ...
Page 96
... Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing FAST INTERRUPT 0 VECTOR ADDRESS LOW 56F8347 Technical Data, Rev. FAST INTERRUPT FAST INTERRUPT 0 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
Page 97
... The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1) Base + $ Read Write RESET Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1) Freescale Semiconductor Preliminary ...
Page 98
... IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number PENDING [16: PENDING [32:17 56F8347 Technical Data, Rev. Freescale Semiconductor Preliminary ...
Page 99
... IRQ Pending (PENDING)—Bits 80–65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor Preliminary PENDING [48:33] ...
Page 100
... This read-only bit reflects the state of the interrupt to the 56800E core. • interrupt is being sent to the 56800E core • interrupt is being sent to the 56800E core 100 VAB INT_DIS 56F8347 Technical Data, Rev. PEND IRQB STATE IRQA STATE IRQB EDG Freescale Semiconductor Preliminary 0 ING [81 IRQA EDG 0 ...
Page 101
... IRQB Edge Pin (IRQB Edg)—Bit 1 This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait modes automatically level-sensitive. • IRQB interrupt is a low-level sensitive (default) • IRQB interrupt is falling-edge sensitive Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Register Descriptions 101 ...
Page 102
... IRQs with fixed priorities: • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. 102 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 103
... Controls reset sequencing after reset • Software-initiated reset • Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control • System Control Register • Registers for software access to the JTAG ID of the chip Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Overview 103 ...
Page 104
... DSP56800E Reference Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR. 104 R/W R Figure 6-1 OMR 56F8347 Technical Data, Rev. R/W R/W R/W R/W R Part 4.2 and Part 7 for detailed Freescale Semiconductor 0 MA R/W X Preliminary ...
Page 105
... SIM_PUDR Base + $A SIM_CLKOSR Base + $B SIM_GPS Base + $C SIM_PCE Base + $D SIM_ISALH Base + $E SIM_ISALL Freescale Semiconductor Preliminary Table 6-1 SIM Registers (SIM_BASE = $00 F350) Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID ...
Page 106
... MODE EBL0 RST DISABLE 0 0 SWR COPR EXTR POR DATA CTRL ADR JTAG TMRD TMRC TMRA 0 A20 CLKDIS CLKOSEL PWM SCI1 SCI0 SPI1 SPI0 ISAL[23:22 EMI_ ONCE SW STOP_ MODE EBL RST DISABLE DISABLE Freescale Semiconductor 1 0 WAIT_ DISABLE PWM WAIT_ 0 Preliminary ...
Page 107
... Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should only clear this register. Base + $ Read Write RESET Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) Freescale Semiconductor Preliminary ...
Page 108
... SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3) Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality. Base + $ Read Write RESET Figure 6-5 SIM Software Control Register 0 (SIM_SCR0) 108 FIELD 56F8347 Technical Data, Rev. Freescale Semiconductor Preliminary 0 0 ...
Page 109
... Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Table 2-2 to identify which pins can deactivate the internal pull-up resistor. Base + $ Read 0 EMI_ PWMA1 CAN MODE Write RESET Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) Freescale Semiconductor Preliminary ...
Page 110
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.13 JTAG—Bit 3 This bit controls the pull-up resistors on the TRST, TMS and TDI pins. 6.5.6.14 Reserved—Bits This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 110 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 111
... Peripheral output function of GPIOB4 is defined to be A20 • Peripheral output function of GPIOB4 is defined to be the prescaler_clock (FREF in 6.5.7.6 Clockout Disable (CLKDIS)—Bit 5 • CLKOUT output is enabled and will output the signal indicated by CLKOSEL • CLKOUT is tri-stated Freescale Semiconductor Preliminary Figure ...
Page 112
... SPI inputs/outputs is made in the SIM_GPS register and in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function of GPIOC[3: programmed as decoder functions. This can be changed by altering the appropriate controls in the indicated registers. 112 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 113
... This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is used for each pin. 2. Reset configuration 3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins. Freescale Semiconductor Preliminary GPIOC_PER Register GPIO Controlled ...
Page 114
... The clocks can be individually controlled for each peripheral on the chip. Base + $ Read EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0 Write RESET Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 114 56F8347 Technical Data, Rev. SPI 1 SPI 0 PWMB Freescale Semiconductor PWMA 1 Preliminary ...
Page 115
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C Enable (TMRC)—Bit 8 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Register Descriptions 115 ...
Page 116
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width Modulator A Enable (PWMA)—0 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 116 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 117
... Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. Freescale Semiconductor Preliminary “ Hard Coded” Address Portion ...
Page 118
... Typically used for power-conscious applications. The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts 3. COP reset 4. External reset 5. Power-on reset 56F8347 Technical Data, Rev. (OCCS), and the 56F8300 . Table 6-3 Description Freescale Semiconductor Preliminary 0 1 ...
Page 119
... Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced to permit proper operation of the device. A POR reset is first extended for 2 stabilization of the clock source, followed clock window in which SIM clocking is initiated then followed clock window in which peripherals are released to implement Flash security, and, Freescale Semiconductor Preliminary D D ...
Page 120
... Secure Mode When Flash security is enabled as described in the Flash Memory module specification, the device will boot in internal boot mode, disable all access to external P-space, and start executing code from the Boot Flash at address 0x02_0000. 120 56F8347 Technical Data, Rev.11 Freescale Semiconductor Preliminary ...
Page 121
... FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values. Freescale Semiconductor Preliminary Figure 7-1. FM_CLKDIV[6] will map to the 56F8347 Technical Data, Rev ...
Page 122
... Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 122 Flash Memory input clock 7 FMCLKD SYS_CLK (2) < < 200[kHz] (DIV + SYS_CLK (2)(8) < < 200[kHz] (DIV + 1) 56F8347 Technical Data, Rev.11 DIVIDER 7 Freescale Semiconductor Preliminary ...
Page 123
... EMI Address pins pins -DEC1 / TMRB / SPI1 pins -DEC0 / TMRA 3 pins -PWMA current sense Freescale Semiconductor Preliminary 4-29 through Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is Peripheral Function 56F8347 Technical Data, Rev.11 Introduction 4-34 define the actual reset values of ...
Page 124
... PWMB current sense SCI0 EMI Address SPI0 TMRC TMRD EMI Data Reset Function EMI Address EMI Address SPI1 DEC0 / TMRA GPIO EMI Chip Selects SCI1 EMI Chip Selects PWMB current sense SCI0 EMI Address SPI0 TMRC GPIO EMI Data Freescale Semiconductor Preliminary ...
Page 125
... Table 8-3 GPIO External Signals Map Pins in italics are NOT available in the 56F8147 device GPIO Port GPIOA GPIOB 1 This is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset. Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 Peripheral 1 Peripheral 2 Peripheral 3 Peripheral 4 Peripheral ...
Page 126
... Index1 / TB2 / MISO1 1 9 Home1 / TB3 / SSI1 PHASEA0 / TA0 155 PHASEB0 / TA1 156 Index0 / TA2 157 Home0 / TA3 158 ISA0 126 ISA1 127 ISA2 128 CS2 55 CS3 56 CS4 57 CS5 58 CS6 59 CS7 60 TXD1 49 RXD1 CS0 CS1 54 ISB0 61 ISB1 63 ISB2 64 Freescale Semiconductor Preliminary ...
Page 127
... Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8147 device GPIO Port GPIOE GPIOF 1. See Part 6.5.8 to determine how to select peripherals from this set Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 Peripheral 1 Peripheral 2 Peripheral 3 Peripheral 4 Peripheral ...
Page 128
... Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. 128 marketing representative are stress ratings only, and functional operation at the maximum CAUTION of any voltages higher 56F8347 Technical Data, Rev.11 or authorized distributor than Freescale Semiconductor Preliminary for ...
Page 129
... Pin Group 6: A6-15, GPIOB0-7, TD0-1 Pin Group 7: CLKO, WR, RD Pin Group 8: PWMA0-5, PWMB0-5 Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST, TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3 Pin Group 10: TCK Pin Group 11: XTAL, EXTAL Pin Group 12: ANA0-7, ANB0-7 Pin Group 13: OCR_DIS, CLKMODE Freescale Semiconductor Preliminary = ( SSA_ADC ...
Page 130
... Technical Data, Rev.11 Typ Max Unit — — V — — V — — Value Value Unit 160-pin LQFP 160MAPBGA 38.5 34.66 °C/W 35.4 31.24 °C/W 33 TBD °C/W 31.5 TBD °C/W 8.6 TBD °C/W 0.8 TBD °C/W User-determined I/O W θ 7 ( Freescale Semiconductor Notes Preliminary ...
Page 131
... Ambient Operating Temperature (Automotive) Ambient Operating Temperature (Industrial) Flash Endurance (Automotive) (Program Erase Cycles) Flash Endurance (Industrial) (Program Erase Cycles) Flash Data Retention Total chip source or sink current cannot exceed 200mA See Pin Groups in Table 10-1 Freescale Semiconductor Preliminary = SSA_ADC , DDA DDA_ADC Symbol ...
Page 132
... IN μA 0 +/- 2 DDA μA 0 +/- DDA μA - μA 0 +/- 2 μA 0 +/- 2 μA 0 +/- 2 μA 0 +/- μA 0 +/- 2 DDA μA 0 +/- 2 DDA μA 200 DDA μA 0 +/- 2 3.0V to OUT 5. — V — — pF — — pF — 6 — pF — 6 — pF — Freescale Semiconductor Preliminary ...
Page 133
... On-Chip Regulator Enabled (OCR_DIS = Low) 1 Mode I DD_IO RUN1_MAC 155mA Wait3 91mA Stop1 5.8mA Stop2 5.1mA 1. No Output Switching 2. Includes Processor Core current supplied by internal voltage regulator Freescale Semiconductor Preliminary Symbol Min POR 1.75 V — EI2.5 V — EI3.3 I bias , an interrupt is generated. EI2 interrupt is generated ...
Page 134
... ADC powered off • PLL powered off • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off Typical Max Unit — 2.75 V — 2.75 V — 2.75 V — 700 mA 5 μ — 30 minutes Freescale Semiconductor Preliminary ...
Page 135
... The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at FMOPT0 and FMOPT1. 3. See Application Note, AN1980, for methods to increase accuracy. 4. Assuming a 12-bit range from 0V to 3.3V. 5. Typical resolution calculated using equation, Freescale Semiconductor Preliminary Table 10-10. PLL Parameters Symbol Min T 0 ...
Page 136
... Figure 10-2 Signal States Symbol Min T 20 prog T 20 erase T 100 me 56F8347 Technical Data, Rev.11 10-5. Unless otherwise specified, High 90% 50% 10% Rise Time and Data3 Valid Data3 Data Active Typ Max Unit μs — — — — ms — — ms Freescale Semiconductor Preliminary ...
Page 137
... The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f the 56F8300 Peripheral User Manual. 3. This is the minimum time required after the PLL set up is changed to ensure reliable operation. Freescale Semiconductor Preliminary Symbol Min ...
Page 138
... Table the EMI quadrature clock is generated using both edges of the EXTAL 56F8347 Technical Data, Rev.11 Typ Max Unit 0. — 120 ohms — 250 ps — 1.5 ns — 300 ps — 300 ps μA 250 290 μA 80 110 μ Figure 10-4 10-16. Freescale Semiconductor Preliminary ...
Page 139
... Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 10-4 External Memory Interface Timing Note: When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. Freescale Semiconductor Preliminary t ARDD t ...
Page 140
... DCAEO WWSH 0.00 RWSH 1.00 RWSS,RWS 1 — N/A 1.00 RWS 1.00 RWSS,RWS 1.25 + DCAOE 0.00 RWSS 1.00 RWSS,RWS 1.25 + DCAOE WWSH,RWSS 0.25 + DCAEO RWSS,RWSH 2 0. MDAR 0.75 + DCAEO WWSS, WWSH 1.00 0.50 RWSH, WWSS, 3 MDAR 0.75 + DCAOE Freescale Semiconductor Preliminary Unit ...
Page 141
... The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. The interrupt instruction fetch is visible on the pins only in Mode 3. Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing ...
Page 142
... A0–A15, PS, DS, RD, WR, t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 10-7 External Level-Sensitive Interrupt Timing 142 IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O 56F8347 Technical Data, Rev.11 t RDA First Fetch Freescale Semiconductor Preliminary ...
Page 143
... Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 10.10 Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Freescale Semiconductor Preliminary t IRI Table 10-18 SPI Timing Symbol Min ELD — ...
Page 144
... Freescale Semiconductor 10-13 10-13 10-13 10-13 10-13 Preliminary ...
Page 145
... MISO (Input) MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-11 SPI Master Timing (CPHA = 1) Freescale Semiconductor Preliminary SS is held High on master MSB in Bits 14– Master MSB out Bits 14– ...
Page 146
... Figure 10-13 SPI Slave Timing (CPHA = 1) 146 ELD Slave MSB out Bits 14– MSB in Bits 14– ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F8347 Technical Data, Rev. ELG Slave LSB out t DI LSB ELG Slave LSB out LSB in Freescale Semiconductor t DI Preliminary ...
Page 147
... Table 10-20 Quadrature Decoder Timing Characteristic Quadrature input period Quadrature input high / low period Quadrature phase period 1. In the formulas listed the clock cycle. For 60MHz operation, T=16.67ns. 2. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary Table 10-19 Timer Timing Symbol Min ...
Page 148
... Table 10-21 SCI Timing Min BR — 0.965/BR PW 0.965/BR PW RXD PW Figure 10-16 RXD Pulse Width TXD PW Figure 10-17 TXD Pulse Width 56F8347 Technical Data, Rev. Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns 10-16 1.04/BR ns 10-17 Freescale Semiconductor Preliminary ...
Page 149
... TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time 1. TCK frequency of operation must be less than 1/8 the processor rate processor clock period (nominally 1/60MHz) Freescale Semiconductor Preliminary Table 10-22 CAN Timing Symbol Min Max — ...
Page 150
... TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-20 Test Access Port Timing Diagram TRST (Input) 150 1 )/ Input Data Valid TRST Figure 10-21 TRST Timing Diagram 56F8347 Technical Data, Rev. Output Data Valid Output Data Valid Freescale Semiconductor Preliminary ...
Page 151
... Quiescent current Uncalibrated Gain Error (ideal = 1) Uncalibrated Offset Voltage 6 Calibrated Absolute Error 7 Calibration Factor 1 7 Calibration Factor 2 Crosstalk between channels Common Mode Voltage Signal-to-noise ratio Signal-to-noise plus distortion ratio Freescale Semiconductor Preliminary Table 10-24 ADC Parameters Symbol Min V V ADIN REFL INL — ...
Page 152
... Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration. 8. ENOB = (SINAD - 1.76)/6.02 152 Symbol Min THD — SFDR — ENOB — .9V in REFH 56F8347 Technical Data, Rev.11 Typ Max Unit 60.6 — db 61.1 — db 9.6 — Bits Freescale Semiconductor Preliminary ...
Page 153
... Although not guaranteed believed that calibration will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes. Freescale Semiconductor Preliminary = 0.60V and 2.70V in 56F8347 Technical Data, Rev ...
Page 154
... These include RAM, Flash memory and the ADCs. 154 / 2, while the other charges to the analog input voltage. When the REFH REFH REFLO 2 S2 56F8347 Technical Data, Rev. The switches switch REFH REFH 1pF Freescale Semiconductor Preliminary ...
Page 155
... For instance, if there is a total of 8 PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. Freescale Semiconductor Preliminary 2 *F CMOS power dissipation corresponding to the Intercept 1 ...
Page 156
... ANB4 ANB3 121 ANB2 ANB1 ANB0 V SSA_ADC V DDA_ADC V REFH V REFP V REFMID V REFN V REFLO TEMP_SENSE ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO V DD_IO V 3* CAP EXTAL XTAL VDDA_OSC_PLL OCR_DIS FAULTA3 D3 FAULTA2 FAULTA1 81 D2 FAULTA0 PWMA5 Freescale Semiconductor Preliminary ...
Page 157
... A10 61 22 A11 62 23 A12 63 24 A13 64 25 A14 65 * When the on-chip regulator is disabled, these four pins become 2.5V V Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name V 81 PWMA5 FAULTA0 DD_IO PWMB3 83 D2 PWMB4 84 FAULTA1 PWMB5 85 FAULTA2 GPIOB5 86 D3 GPIOB6 87 FAULTA3 ...
Page 158
... ANB4 SS 56F8347 Technical Data, Rev.11 Pin No. Signal Name 146 SCLK0 147 MISO0 148 MOSI0 149 D11 150 D12 151 D13 152 D14 153 D15 154 A0 155 PHASEA0 156 PHASEB0 157 INDEX0 158 HOME0 159 EMI_MODE 160 V SS Freescale Semiconductor Preliminary ...
Page 159
... A15 GPIOB0 GPIOB2 GPIOB1 M GPIOB3 GPIOB4 GPIOB7 PWMB5 N PWMB0 PWMB2 PWMB3 GPIOB5 P PWMB1 PWMB4 GPIOB6 TXD1 Figure 11-2 Top View, 56F8347 160-Pin MAPBGA Package Freescale Semiconductor Preliminary D12 V 1 D11 SCLK0 TMS PP D13 MOSI0 CAN_RX TDI D14 SS0 CAN_TX TDO TCK ...
Page 160
... Signal Name No. A13 ANB5 B12 ANB6 A12 ANB7 B11 EXTBOOT J11 V SS A11 ISA0 C11 ISA1 D11 ISA2 B10 TD0 A10 TD1 D10 TD2 E10 TD3 A9 TC0 F11 V DD_IO B9 TC1 D9 TRST D8 TCK A8 TMS B8 TDI D7 TDO CAN_TX B7 CAN_RX CAP D5 SS0 . Freescale Semiconductor Preliminary ...
Page 161
... D10 P11 L1 GPIOB0 M11 L3 GPIOB1 G11 L2 GPIOB2 P12 M1 GPIOB3 N11 M2 GPIOB4 E9 N1 PWMB0 M12 P1 PWMB1 P13 N2 PWMB2 E7 Freescale Semiconductor Preliminary Ball Signal Name Signal Name No. IRQB G14 ANA6 FAULTB0 E13 ANA7 FAULTB1 E11 TEMP_SENSE FAULTB2 E12 V REFLO D0 F14 V REFN D1 E14 V REFMID ...
Page 162
... PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS DIM MIN MAX A 1.32 1.75 A1 0.27 0.47 A2 1.18 REF b 0.35 0.65 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC 5 0. 160X DETAIL K ° ROTATED 90 CLOCKWISE DATE 04/06/98 Freescale Semiconductor Preliminary ...
Page 163
... GPIOB4 PWMB0 41 PWMB1 PWMB2 * When the on-chip regulator is disabled, these four pins become 2.5V V Figure 11-4 Top View, 56F8147 160-Pin LQFP Package Freescale Semiconductor Preliminary Figure 11-4 shows the package outline for the 160-pin LQFP, . DD_CORE 56F8347 Technical Data, Rev.11 56F8147 Package and Pin-Out Information ...
Page 164
... GPIOC8 127 GPIOC9 128 GPIOC10 129 GPIOE10 130 GPIOE11 131 GPIOE12 132 GPIOE13 133 TC0 134 V DD_IO 3* 135 TC1 136 TRST 137 TCK 138 TMS 139 TDI 140 TDO 141 142 NC 143 NC 144 V 2* CAP 145 SS0 Freescale Semiconductor Preliminary ...
Page 165
... D10 72 33 GPIOB0 73 34 GPIOB1 74 35 GPIOB2 75 36 GPIOB3 76 37 GPIOB4 77 38 PWMB0 78 39 PWMB1 79 40 PWMB2 80 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name IRQB 106 ANA6 FAULTB0 107 ANA7 FAULTB1 108 NC FAULTB2 109 V REFLO D0 110 V REFN D1 111 V REFMID FAULTB3 ...
Page 166
... D 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 24.00 BSC L 0.45 0.75 L1 1.00 REF R1 0.08 --- R2 0.08 0.20 S 0.20 --- ° ° θ ° θ --- ° ° θ ° ° θ Freescale Semiconductor Preliminary ...
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... D where Thermocouple temperature on top of package ( T Ψ = Thermal characterization parameter ( Power dissipation in package (W) D Freescale Semiconductor Preliminary , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with a JT ...
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... Ceramic and tantalum capacitors tend to provide better DDA SSA. layers of the PCB with approximately 100μF, preferably with a high-grade 56F8347 Technical Data, Rev.11 higher than pin on the device, and from the DD and V (GND and Freescale Semiconductor Preliminary ...
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... Flash, RAM and internal logic are powered from the core regulator output • and V 2 are not connected in the customer system PP PP • All circuitry, analog and digital, shares a common V V DDA_OSC_PLL REG OSC Freescale Semiconductor Preliminary , V REF DDA pins. bus CAP REG ...
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... Technical Data, Rev.11 Ambient Temperature Order Number (MHz) Range 60 -40° 105°C MC56F8347VPY60 40 -40° 105°C MC56F8147VPY 60 -40° 105°C MC56F8347VPYE* 60 -40° 125°C MC56F8347MPYE* 40 -40° 105°C MC56F8147VPYE* 60 -40° 105°C MC56F8347VVF* Freescale Semiconductor Preliminary ...
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... Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Power Distribution and I/O Ring Implementation 171 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...