MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 96

IC DSP 16BIT 40MHZ 160-LQFP

MC56F8147VPYE

Manufacturer Part Number
MC56F8147VPYE
Description
IC DSP 16BIT 40MHZ 160-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet

Specifications of MC56F8147VPYE

Core Processor
56800
Core Size
16-Bit
Speed
40MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
76
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
160-LQFP
Data Bus Width
16 bit
Processor Series
MC56F81xx
Core
56800E
Data Ram Size
4 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
76
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
4 x 12 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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5.6.12
5.6.12.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see
occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to
5.6.13
5.6.13.1
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.14
5.6.14.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
96
Base + $B
Base + $C
Base + $D
RESET
RESET
RESET
Write
Write
Write
Read
Read
Read
Part
Fast Interrupt 0 Match Register (FIM0)
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Fast Interrupt 0 Vector Address High Register (FIVAH0)
Reserved—Bits 15–7
Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Reserved—Bits 15–5
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Table
5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will
15
15
15
0
0
0
0
0
4-5.
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
14
14
14
0
0
0
0
0
13
13
13
0
0
0
0
0
12
12
12
0
0
0
0
0
56F8347 Technical Data, Rev.11
11
11
11
0
0
0
0
0
10
10
10
0
0
0
0
0
VECTOR ADDRESS LOW
9
0
0
9
0
9
0
0
FAST INTERRUPT 0
8
0
0
8
0
8
0
0
7
7
7
0
0
0
0
0
6
6
6
0
0
0
0
5
0
5
0
5
0
0
FAST INTERRUPT 0
4
4
4
0
0
0
VECTOR ADDRESS HIGH
FAST INTERRUPT 0
3
3
3
0
0
0
Freescale Semiconductor
2
0
2
0
2
0
1
0
1
0
1
0
Preliminary
0
0
0
0
0
0

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