MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 27

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
(GPIOD6)
(GPIOD7)
RXD1
TXD1
TMS
TDO
TCK
TDI
137
138
139
140
Pin
No.
49
50
Ball
No.
N5
D8
D7
P4
A8
B8
Schmitt
Schmitt
Schmitt
Output
Output
Output
Output
Input/
Input/
Type
Input
Input
Input
Input
56F8347 Technical Data, Rev.11
pulled low
disabled,
pull-up is
internally
internally
internally
disabled,
pull-up is
output is
output is
In reset,
enabled
enabled
In reset,
enabled
During
pull-up
Reset
pulled
pulled
Input,
Input,
Input,
Input,
State
high
high
Test Data Input — This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in
the SIM_PUDR register.
Test Data Output — This tri-stateable output pin provides a
serial output data stream from the JTAG/EOnCE port. It is
driven in the shift-IR and shift-DR controller states, and
changes on the falling edge of TCK.
Transmit Data — SCI1 transmit data output
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
Receive Data — SCI1 receive data input
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the
JTAG/EOnCE port. The pin is connected internally to a
pull-down resistor.
Test Mode Select Input — This input pin is used to
sequence the JTAG TAP controller’s state machine. It is
sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in
the SIM_PUDR register.
Note:
Always tie the TMS pin to V
Signal Description
DD
through a 2.2K resistor.
Signal Pins
27