MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 47

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1. The SYS_XTAL_IN frequency, Sys PLL, and Core PLL settings must be chosen so that the resulting e300 clk, csb_clk, and
2. The values are valid for the user-operation mode. There can be deviations for test modes.
3. When selecting the peripheral clock frequencies, care needs to be taken about requirements for baud rates and minimum
4.The DDR data rate is 2x the DDR memory bus frequency.
SYS_XTAL_IN is the input clock multiplied by the system phase-locked loop (Sys PLL) and the clock unit to create the coherent
system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the clocks for the peripherals.The csb_clk
serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the
internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields
in the reset configuration word, which is loaded at power-on reset.
See the MPC5125 Reference Manual (MPC5125RM)
4.3.3
The MPC5125 has three reset pins:
These signals are asynchronous I / O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires
the same input characteristics as other MPC5125 inputs, as specified in
As long as VDD is not stable the HRESET output is not stable.
The timing relationship can be seen in the following figures.
Freescale Semiconductor
MCK frequencies do not exceed their respective maximum or minimum operating frequencies.
frequency limitation.
•
•
•
PORESET — Power-on reset
HRESET — Hard reset
SRESET — Software reset
Resets
NOTES:
1
2
3
PORESET
PORESET rise time
HRESET
HRESET rise time
SRESET fall time
SRESET rise time
Make sure that the PORESET does not carry any glitches. The MPC5125 has no
filter to prevent them from getting into the chip.
HRESET and SRESET must have a monotonous rise time.
The assertion of HRESET becomes active at power-on reset without any
SYS_XTAL clock.
2,3
Description
1
fall time
fall time
MPC5125 Microcontroller Data Sheet, Rev. 3
Table 18. Reset Rise / Fall Timing
, for more information on the clock subsystem.
Min
—
—
—
—
—
—
Section 4.1, “DC Electrical
Max
1
1
1
1
1
1
Electrical and Thermal Characteristics
Unit
ms
ms
ms
ms
ms
ms
SpecID
A3.4
A3.5
A3.6
A3.7
A3.8
A3.9
Characteristics.”
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