MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 50

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NOTES:
1
Electrical and Thermal Characteristics
4.3.4
The MPC5125 provides three different kinds of external interrupts:
IPIC inputs must be valid for at least t
4.3.5
The MPC5125 memory controller supports these types of DDR devices:
JEDEC standards define the minimum set of requirements for compliant memory devices:
The MPC5125 supports the configuration of two output drive strengths for DDR2 and LPDDR:
The MPC5125 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device.
This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in
Electrical Characteristics.”
50
t
The timings will change when using the PLL lock detection circuit.
t
HR_SR_DELAY
H_POR_CONF
•
•
•
•
•
•
•
•
•
•
•
•
t
Symbol
t
HRHOLD
SRHOLD
t
SRMIN
GPIO interrupts with simple interrupt capability (not available in power-down mode)
Wakeup interrupts
DDR-1 (SSTL_2 class II interface)
DDR-2 (SSTL_18 interface)
LPDDR (1.8V I/O supply voltage)
SDR D-RAM
JEDEC standard, DDR2 SDRAM specification, JESD79-2C, May 2006
JEDEC standard, Double Data Rate (DDR) SDRAM specification, JESD79E, May 2005
JEDEC standard, Low Power Double Data Rate (LPDDR) SDRAM specification, JESD79-4, May 2006
Full drive strength
Half drive strength (intended for lighter loads or point-to-point environments)
IRQ interrupts
External Interrupts
SDRAM (DDR)
IPIC inputs — minimum pulse width
Reset configuration hold time after assertion of PORESET.
Time from falling edge of HRESET to falling edge of SRESET.
Time HRESET must be held low before a qualified reset occurs.
Time SRESET must be held low before a qualified reset occurs.
Time SRESET is asserted after it has been qualified.
Descriptions
Table 20. IPIC Input AC Timing Specifications
PICWID
MPC5125 Microcontroller Data Sheet, Rev. 3
Table 19. Reset Timing (continued)
to ensure proper operation in edge-triggered mode.
Description
Symbol
t
PICWID
Min
2T
Unit
ns
Spec ID
A4.1
(XTALI CLOCK)
Freescale Semiconductor
4 cycles
4 cycles
4 cycles
1 cycles
1 cycle
Value
Section 4.1, “DC
SpecID
A3.16
A3.17
A3.18
A3.19
A3.15