MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 83

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4
The MPC5125 requires external pullup or pulldown resistors on certain pins.
5.4.1
The MPC5125 requires a pulldown resistor on the test pin TEST.
5.5
The MPC5125 has an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a common on-chip
processor (COP) interface, which shares the IEEE 1149.1 JTAG port.
The COP interface provides access to the MPC5125’s embedded e300 processor and to other on-chip resources. This interface
provides a means for executing test routines and for performing software development and debug functions.
5.5.1
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
5.5.1.1
The JTAG interface can control the direction of the MPC5125 I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5125 comes out of power-on reset; do this by asserting TRST before PORESET is released.
For more details, see the Reset and JTAG Timing Specification.
5.5.2
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
5.5.2.1
The MPC5125 functional pin interface and internal logic provides access to the embedded e300 processor core through the
Freescale standard COP / BDM interface.
COP / BDM connector order.
Freescale Semiconductor
Required assertion of TRST
PORESET
Pullup/Pulldown Resistor Requirements
JTAG
Pulldown Resistor Requirements for TEST Pin
JTAG_TRST
e300 COP / BDM Interface
TRST and PORESET
Boards Interfacing the JTAG Port via a COP Connector
TRST
MPC5125 Microcontroller Data Sheet, Rev. 3
Table 49
Figure 50. PORESET vs. TRST
gives the COP / BDM interface signals. The pin order shown reflects only the
Optional assertion of TRST
System Design Information
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