MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 70

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical and Thermal Characteristics
NOTES:
1
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H
parameters are programmed via the HSYN_PARA register; and the PW_V, BP_V, and FP_V parameters are programmed via
the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions of these parameters.
Figure 36
70
Parameter
Display interface pixel clock period immediate value (in nanoseconds).
t
t
t
t
t
t
DHD
CHD
CKH
DSU
CSU
CKL
Sym
t
t
t
t
t
t
t
PWV
FPH
HSP
BPV
t
VSP
FPV
SW
SH
depicts the synchronous display interface timing for access level, and
DIU_HSYNC
DIU_VSYNC
DIU_DE
DIU_CLK
DIU_LD[23:0]
LCD interface pixel clock high time
LCD interface pixel clock low time
LCD interface data setup time
LCD interface data hold time
LCD interface control signal setup time
LCD interface control signal hold time
HSYNC Front Porch Width
Screen Width
HSYNC (Line) Period
VSYNC Pulse Width
VSYNC Back Porch Width
VSYNC Front Porch Width
Screen Height
VSYNC (Frame) Period
Description
Table 36. LCD Interface Timing Parameters — Access Level
Description
Figure 36. LCD Interface Timing Diagram — Access Level
Table 35. LCD Interface Timing Parameters — Pixel Level
t
CKH
MPC5125 Microcontroller Data Sheet, Rev. 3
t
CKL
FP_H × t
DELTA_X × t
PW_V × t
BP_V × t
FP_V × t
DELTA_Y × t
(PW_H + BP_H + DELTA_X + FP_H) × t
(PW_V + BP_V + DELTA_Y + FP_H) × t
t
t
PCP
PCP
HSP
PCP
HSP
HSP
Min
5.0
6.0
5.0
6.0
PCP
HSP
× 0.4
× 0.4
t
t
DHD
CHD
Value
t
t
PCP
PCP
Typ
—
t
t
—
—
—
CSU
DSU
× 0.5
× 0.5
Table 36
t
t
PCP
PCP
lists the timing parameters.
Max
HSP
—
—
—
—
PCP
× 0.6
× 0.6
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
Unit
Unit
ns
ns
ns
ns
ns
ns
A15.12
A15.13
A15.14
A15.15
A15.16
A15.17
A15.4
A15.5
A15.6
A15.7
A15.8
A15.9
A15.10
A15.11
SpecID
SpecID