ATTINY9-TSHR Atmel, ATTINY9-TSHR Datasheet - Page 108
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ATTINY9-TSHR
Manufacturer Part Number
ATTINY9-TSHR
Description
IC MCU AVR 1KB FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY9-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
1KB (1K x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY9x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-TSHR
Manufacturer:
RFMD
Quantity:
5 000
15. Memory Programming
15.1
15.2
108
Features
Overview
ATtiny4/5/9/10
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The Non-Volatile Memory (NVM) Controller manages all access to the Non-Volatile Memories.
The NVM Controller controls all NVM timing and access privileges, and holds the status of the
NVM.
During normal execution the CPU will execute code from the code section of the Flash memory
(program memory). When entering sleep and no programming operations are active, the Flash
memory is disabled to minimize power consumption.
All NVM are mapped to the data memory. Application software can read the NVM from the
mapped locations of data memory using load instruction with indirect addressing.
The NVM has only one read port and, therefore, the next instruction and the data can not be
read simultaneously. When the application reads data from NVM locations mapped to the data
space, the data is read first before the next instruction is fetched. The CPU execution is here
delayed by one system clock cycle.
Internal programming operations to NVM have been disabled and the NVM therefore appears to
the application software as read-only. Internal write or erase operations of the NVM will not be
successful.
The method used by the external programmer for writing the Non-Volatile Memories is referred
to as external programming. External programming can be done both in-system or in mass pro-
duction. See
via the Tiny Programming Interface (TPI).
In the external programming mode all NVM can be read and programmed, except the signature
and the calibration sections which are read-only.
NVM can be programmed at 5V, only.
Two Embedded Non-Volatile Memories:
Four Separate Sections Inside Flash Memory:
Read Access to All Non-Volatile Memories from Application Software
Read and Write Access to Non-Volatile Memories from External programmer:
External Programming:
High Security with NVM Lock Bits
– Non-Volatile Memory Lock bits (NVM Lock bits)
– Flash Memory
– Code Section (Program Memory)
– Signature Section
– Configuration Section
– Calibration Section
– Read Access to All Non-Volatile Memories
– Write Access to NVM Lock Bits, Flash Code Section and Flash Configuration Section
– Support for In-System and Mass Production Programming
– Programming Through the Tiny Programming Interface (TPI)
Figure 14-2 on page
98. The external programmer can read and program the NVM
8127D–AVR–02/10