ATTINY9-TSHR Atmel, ATTINY9-TSHR Datasheet - Page 77
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ATTINY9-TSHR
Manufacturer Part Number
ATTINY9-TSHR
Description
IC MCU AVR 1KB FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY9-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
1KB (1K x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY9x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-TSHR
Manufacturer:
RFMD
Quantity:
5 000
11.11.3
8127D–AVR–02/10
TCCR0C – Timer/Counter0 Control Register C
When a capture is triggered according to the ICES0 setting, the counter value is copied into the
Input Capture Register (ICR0). The event will also set the Input Capture Flag (ICF0), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR0 is used as TOP value (see description of the WGM03:0 bits located in the
TCCR0A and the TCCR0B Register), the ICP0 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR0B is written.
• Bits 4:3 – WGM03:2: Waveform Generation Mode
See
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits set the clock source to be used by the Timer/Counter, see
12
Table 11-6.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOC0A: Force Output Compare for Channel A
• Bit 6 – FOC0B: Force Output Compare for Channel B
The FOC0A/FOC0B bits are only active when the WGM03:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR0A is written when operating in a PWM mode. When writing a logical one to the
FOC0A/FOC0B bit, an immediate compare match is forced on the Waveform Generation unit.
Bit
0x2C
Read/Write
Initial Value
CS02
and
0
0
0
0
1
1
1
1
“TCCR0A – Timer/Counter0 Control Register A” on page
Figure
CS01
11-13.
0
0
1
1
0
0
1
1
Clock Select Bit Description
FOC0A
W
7
0
CS00
FOC0B
0
1
0
1
0
1
0
1
W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge
External clock source on T0 pin. Clock on rising edge
I/O
I/O
I/O
I/O
I/O
R
5
–
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R
4
–
0
R
3
–
0
74.
R
2
–
0
ATtiny4/5/9/10
R
1
–
0
R
0
–
0
Figure 11-
TCCR0C
77