ATTINY9-TSHR Atmel, ATTINY9-TSHR Datasheet - Page 16
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ATTINY9-TSHR
Manufacturer Part Number
ATTINY9-TSHR
Description
IC MCU AVR 1KB FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY9-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
1KB (1K x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY9x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-TSHR
Manufacturer:
RFMD
Quantity:
5 000
5.3
I/O Memory
The I/O space definition of the ATtiny4/5/9/10 is shown in
“Register Summary” on page
150.
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed using the LD and ST instructions, enabling data transfer between the 16 general pur-
pose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of sin-
gle bits can be checked by using the SBIS and SBIC instructions. See document “AVR
Instruction Set” and section
“Instruction Set Summary” on page 152
for more details. When
using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such status flags. The CBI and SBI instructions work on registers in the address range 0x00
to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
ATtiny4/5/9/10
16
8127D–AVR–02/10