ATTINY9-TSHR Atmel, ATTINY9-TSHR Datasheet - Page 64
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ATTINY9-TSHR
Manufacturer Part Number
ATTINY9-TSHR
Description
IC MCU AVR 1KB FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY9-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
1KB (1K x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY9x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-TSHR
Manufacturer:
RFMD
Quantity:
5 000
11.8.3
64
ATtiny4/5/9/10
Fast PWM Mode
The timing diagram for the CTC mode is shown in
(TCNT0) increases until a compare match occurs with either OCR0A or ICR0, and then counter
(TCNT0) is cleared.
Figure 11-8. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF0A or ICF0 flag according to the register used to define the TOP value. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCR0A or ICR0 is lower than the current value of TCNT0, the
counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCR0A for defining TOP (WGM03:0 = 15) since the OCR0A then will be double buffered.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OC0A = 1). The waveform generated will have a maximum fre-
quency of
by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
The fast Pulse Width Modulation or fast PWM mode (WGM03:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared
on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare
Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope
TCNTn
OCnA
(Toggle)
Period
0
A
= f
clk_I/O
1
/2 when OCR0A is set to zero (0x0000). The waveform frequency is defined
f
OCnA
2
=
---------------------------------------------------
2 N
3
⋅
⋅
(
f
1
clk_I/O
+
Figure 11-8 on page
4
OCRnA
)
64. The counter value
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnA1:0 = 1)
8127D–AVR–02/10