ATTINY9-TSHR Atmel, ATTINY9-TSHR Datasheet - Page 24
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ATTINY9-TSHR
Manufacturer Part Number
ATTINY9-TSHR
Description
IC MCU AVR 1KB FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY9-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
1KB (1K x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY9x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-TSHR
Manufacturer:
RFMD
Quantity:
5 000
7.1.2
7.1.3
7.1.4
7.2
7.3
24
Power Reduction Register
Minimizing Power Consumption
ATtiny4/5/9/10
ADC Noise Reduction Mode
Power-down Mode
Standby Mode
analog comparator can be powered down by setting the ACD bit in
Control and Status Register” on page
ADC is enabled (ATtiny5/10, only), a conversion starts automatically when this mode is entered.
When bits SM2:0 are written to 001, the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the watch-
dog to continue operating (if enabled). This sleep mode halts clk
allowing the other clocks to run.
This mode improves the noise environment for the ADC, enabling higher resolution measure-
ments. If the ADC is enabled, a conversion starts automatically when this mode is entered.
This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC.
When bits SM2:0 are written to 010, the SLEEP instruction makes the MCU enter Power-down
mode. In this mode, the oscillator is stopped, while the external interrupts, and the watchdog
continue operating (if enabled). Only a watchdog reset, an external level interrupt on INT0, or a
pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing
operation of asynchronous modules only.
When bits SM2:0 are written to 100, the SLEEP instruction makes the MCU enter Standby
mode. This mode is identical to Power-down with the exception that the oscillator is kept run-
ning. This reduces wake-up time, because the oscillator is already running and doesn't need to
be started up.
The Power Reduction Register (PRR), see
vides a method to reduce power consumption by stopping the clock to individual peripherals.
When the clock for a peripheral is stopped then:
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit
wakes up the peripheral and puts it in the same state as before shutdown.
Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the over-
all power consumption. See
other sleep modes, the clock is already stopped.
There are several issues to consider when trying to minimize the power consumption in an AVR
Core controlled system. In general, sleep modes should be used as much as possible, and the
sleep mode should be selected so that as few as possible of the device’s functions are operat-
ing. All functions not needed should be disabled. In particular, the following modules may need
special consideration when trying to achieve the lowest possible power consumption.
• The current state of the peripheral is frozen.
• The associated registers can not be read or written.
• Resources used by the peripheral will remain occupied.
“Supply Current of I/O Modules” on page 123
82. This will reduce power consumption in idle mode. If the
“PRR – Power Reduction Register” on page
“ACSR – Analog Comparator
I/O
, clk
CPU
for examples. In all
, and clk
8127D–AVR–02/10
NVM
26, pro-
, while