ATTINY9-TSHR Atmel, ATTINY9-TSHR Datasheet - Page 94
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATTINY9-TSHR
Manufacturer Part Number
ATTINY9-TSHR
Description
IC MCU AVR 1KB FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY9-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
1KB (1K x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY9x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-TSHR
Manufacturer:
RFMD
Quantity:
5 000
13.12 Register Description
13.12.1
13.12.2
94
ATtiny4/5/9/10
ADMUX
ADCSRA
–
–
ADC Multiplexer Selection Register
ADC Control and Status Register A
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 1:0 – MUX1:0: Analog Channel Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
See
in effect until the conversion is complete (ADIF in ADCSRA is set).
Table 13-2.
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
Bit
0x1B
Read/Write
Initial Value
Bit
0x1D
Read/Write
Initial Value
Table 13-2
MUX1
0
1
ADEN
R/W
Input Channel Selections
7
0
R
7
–
0
for details. If these bits are changed during a conversion, the change will not go
ADSC
R/W
6
0
R
6
–
0
ADATE
R/W
5
0
R
5
–
0
MUX0
0
1
0
1
ADIF
R/W
4
0
R
4
–
0
ADIE
R/W
3
0
3
–
R
0
Single Ended Input
ADC0 (PB0)
ADC1 (PB1)
ADC2 (PB2)
ADC3 (PB3)
ADPS2
R/W
2
0
R
2
–
0
ADPS1
R/W
MUX1
1
0
R/W
1
0
ADPS0
R/W
MUX0
0
0
R/W
0
0
ADCSRA
ADMUX
8127D–AVR–02/10