ATTINY2313A-MUR Atmel, ATTINY2313A-MUR Datasheet - Page 121
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ATTINY2313A-MUR
Manufacturer Part Number
ATTINY2313A-MUR
Description
MCU AVR 2K FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY2313A-MU.pdf
(270 pages)
Specifications of ATTINY2313A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY2313A-MUR
Manufacturer:
LT
Quantity:
4 439
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14.3.1
8246A–AVR–11/09
Internal Clock Generation – The Baud Rate Generator
Figure 14-2. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits.
Table 14-1
ing the UBRR value for each mode of operation using an internally generated clock source.
osc
), is loaded with the UBRR value each time the counter has counted down to zero or when
txclk
rxclk
xcki
xcko
fosc
DDR_XCK
XCK
Pin
contains equations for calculating the baud rate (in bits per second) and for calculat-
xcko
xcki
OSC
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/2
Figure
osc
/(UBRR+1)). The Transmitter divides the
/4
14-2.
/2
DDR_XCK
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
121
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