ATTINY2313A-MUR Atmel, ATTINY2313A-MUR Datasheet - Page 59
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ATTINY2313A-MUR
Manufacturer Part Number
ATTINY2313A-MUR
Description
MCU AVR 2K FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY2313A-MU.pdf
(270 pages)
Specifications of ATTINY2313A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY2313A-MUR
Manufacturer:
LT
Quantity:
4 439
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10.2
8246A–AVR–11/09
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. In
below is shown how the port pin control signals from the simplified
be overridden by alternate functions.
Figure 10-5. Alternate Port Functions
Note:
The illustration in the figure above serves as a generic description applicable to all port pins in
the AVR microcontroller family. Some overriding signals may not be present in all port pins.
PTOExn:
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
Pxn, PORT TOGGLE OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
SLEEP CONTROL
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
1
0
1
0
1
0
1
0
PUOExn
PUOVxn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
(1)
SYNCHRONIZER
D
L
SET
CLR
Q
Q
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
clk
DIxn:
AIOxn:
D
PINxn
CLR
I/O
Q
Q
:
RESET
PORTxn
Q
Q
CLR
D
RESET
Q
Q
DDxn
CLR
WRITE DDRx
WRITE PORTx
PULLUP DISABLE
READ DDRx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
D
1
0
RRx
Figure 10-2 on page 55
clk
PUD
WDx
RDx
DIxn
AIOxn
RPx
I/O
WRx
PTOExn
WPx
Figure 10-5
I/O
,
can
59
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