ATTINY2313A-MUR Atmel, ATTINY2313A-MUR Datasheet - Page 42

• Manufacturer Part Number: ATTINY2313A-MUR
• Description: MCU AVR 2K FLASH 20MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

8.4.1
42
ATtiny2313A/4313
Timed Sequences for Changing the Configuration of the Watchdog Timer
The Watchdog Timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
Sequences for Changing the Configuration of the Watchdog Timer” on page 42
Table 8-1.
Figure 8-7.
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
WDTON
Unprogrammed
Programmed
• Safety Level 1
• Safety Level 2
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the
WDE bit to one without any restriction. A timed sequence is needed when disabling an
enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure
must be followed:
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as
one. A timed sequence is needed when changing the Watchdog Time-out period. To change
the Watchdog Time-out, the following procedure must be followed:
a. In the same operation, write a logic one to WDCE and WDE. A logic one must be
b. Within the next four clock cycles, in the same operation, write the WDE and WDP
written to WDE regardless of the previous value of the WDE bit
bits as desired, but with the WDCE bit cleared
WDT Configuration as a Function of the Fuse Settings of WDTON
Watchdog Timer
Safety
Level
WATCHDOG
1
2
OSCILLATOR
RESET
128 kHz
WDP0
WDP1
WDP2
WDP3
WDE
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
MCU RESET
PRESCALER
WATCHDOG
MUX
Table 8-1
How to Change Time-
out
No limitations
Timed sequence
for details.
8246A–AVR–11/09
See
“Timed