ATTINY48-MMHR Atmel, ATTINY48-MMHR Datasheet - Page 117

• Manufacturer Part Number: ATTINY48-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 28QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. Timer/Counter0 and Timer/Counter1 Prescalers
13.1
13.2
13.3
8008G–AVR–04/11
Internal Clock Source
Prescaler Reset
External Clock Source
“8-bit Timer/Counter0” on page 80
same prescaler module, but the Timer/Counters can have different prescaler settings. The
description below applies to both Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (CSn[2:0] = 0b010, 0b011, 0b100, or 0b101).
The number of system clock cycles from when the timer is enabled to the first count occurs can
be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or
1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (
is transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn[2:0] = 6) edge it detects.
Figure 13-1. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
CLK_I/O
Tn
T1
clk
/clk
I/O
/256, or f
T0
). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
CLK_I/O
D
LE
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be used
and
T1
“16-bit Timer/Counter1 with PWM” on page 89
/clk
T
0
pulse for each positive (CSn[2:0] = 7) or negative
D
Q
ATtiny48/88
CLK_I/O
Edge Detector
clk
/8, f
I/O
Figure 13-1
). The latch
CLK_I/O
share the
Tn_sync
(To Clock
Select Logic)
/64,
117