ATTINY48-MMHR Atmel, ATTINY48-MMHR Datasheet - Page 170

• Manufacturer Part Number: ATTINY48-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 28QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.6
17.6.1
170
Changing Channel or Reference Selection
ATtiny48/88
ADC Input Channels
For a summary of conversion times, see
Table 17-1.
Bits MUXn and REFS0 in the ADMUX Register are single buffered through a temporary register
to which the CPU has random access. This ensures that the channels and reference selection
only takes place at a safe point during the conversion. The channel and reference selection is
continuously updated until a conversion is started. Once the conversion starts, the channel and
reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous
updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADC-
SRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is
written. The user is thus advised not to write new channel or reference selection values to
ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Free Running conversions
• When ADATE or ADEN is cleared.
• During conversion, minimum one ADC clock cycle after the trigger event.
• After a conversion, before the Interrupt Flag used as trigger source is cleared.
ADC Conversion Time
Sample & Hold
(Cycles from Start of Conversion)
Table
17-1.
13.5
1.5
2.5
2
Conversion Time
(Cycles)
13.5
25
13
14
8008G–AVR–04/11