ATTINY48-MMHR Atmel, ATTINY48-MMHR Datasheet - Page 118

• Manufacturer Part Number: ATTINY48-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 28QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4
13.4.1
118
Register Description
ATtiny48/88
GTCCR – General Timer/Counter Control Register
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by oscillator source tolerances, it is recommended that maximum fre-
quency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can
be configured to the same value without the risk of one of them advancing during configuration.
PSRSYNC
Bit
0x23 (0x43)
Read/Write
Initial Value
clk
T0
T1
I/O
1. The synchronization logic on the input pins (
Synchronization
Synchronization
TSM
R/W
7
0
ExtClk
R
6
–
0
< f
clk_I/O
R
5
–
0
/2) given a 50% duty cycle. Since the edge detector uses
clk
Clear
T1
R
4
–
0
clk_I/O
T1/T0)
R
3
–
0
/2.5.
is shown in
R
2
–
0
(1)
Figure
R
1
–
0
13-1.
PSRSYNC
clk
R/W
0
0
T0
8008G–AVR–04/11
GTCCR