ATA6612P-PLPW Atmel, ATA6612P-PLPW Datasheet - Page 194
ATA6612P-PLPW
Manufacturer Part Number
ATA6612P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Atmel ATA6612/ATA6613
Figure 6-69. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed
from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all
units. The Clock Generation logic consists of synchronization logic for external clock input
used by synchronous slave operation, and the baud rate generator. The XCKn (Transfer
Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single
write buffer, a serial Shift Register, Parity Generator and Control logic for handling different
serial frame formats. The write buffer allows a continuous transfer of data without any delay
between frames. The Receiver is the most complex part of the USART module due to its clock
and data recovery units. The recovery units are used for asynchronous data reception. In addi-
tion to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift
Register and a two level receive buffer (UDRn). The Receiver supports the same frame for-
mats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.
1. Refer to
Table 6-38 on page 104
UCSRnA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn(Receive)
UDRn(Transmit)
UBRRn [H:L]
(1)
for USART0 pin placement.
UCSRnB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
Clock Generator
Transmitter
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Receiver
PIN
PIN
PIN
TX
RX
UCSRnC
9111H–AUTO–01/11
XCKn
TxDn
RxDn
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